參數(shù)資料
型號: HD66727
廠商: Hitachi,Ltd.
英文描述: Low-Power Dot-Matrix Liquid Crystal Display Controller/Driver with Key Scan Function(帶鍵掃描功能的圖形LCD控制器/驅(qū)動器)
中文描述: 低功耗點陣液晶顯示控制器/鍵掃描功能(帶鍵掃描功能的圖形液晶顯示控制器/驅(qū)動器驅(qū)動程序)
文件頁數(shù): 42/98頁
文件大?。?/td> 1576K
代理商: HD66727
HD66727
42
IRE:
When IRE is 1, the key scan interrupt (IRQ*) generation is enabled. When a key is pressed, the IRQ*
pin outputs a low level signal.
KF1, KF0:
Used for specifying the key scan cycle. Set these bits according to the mechanical
characteristics of the keys and the oscillation frequency (Table 22).
Table 22
KF Bits and Key Scan Cycles
NL1
KF1
KF0
Key Scan Cycle
Key Strobe Width
1 or 2 display lines (NL1=0)
0
0
160/fosc
20/fosc
1 or 2 display lines (NL1=0)
0
1
320/fosc
40/fosc
1 or 2 display lines (NL1=0)
1
0
640/fosc
80/fosc
1 or 2 display lines (NL1=0)
1
1
1,280/fosc
160/fosc
3 or 4 display lines (NL1=1)
0
0
320/fosc
40/fosc
3 or 4 display lines (NL1=1)
0
1
640/fosc
80/fosc
3 or 4 display lines (NL1=1)
1
0
1,280/fosc
160/fosc
3 or 4 display lines (NL1=1)
Note:
fosc is the oscillation frequency or external clock frequency.
1
1
2,560/fosc
320/fosc
Write Data to RAM
The write data to RAM instruction (Figure 21) writes 8-bit data to annunciator or DDRAM, lower 6-bit
data to LED port, SEGRAM or CGRAM, or lower two bits to shift direction change bits of SEG/COM that
is selected by the previous specification of the address set instruction (annunciator/LED/SEGRAM address
set, CGRAM address set, or DDRAM address set).
After a write, the address is automatically incremented or decremented by 1 according to the I/D bit setting
in the entry mode set instruction. The annunciator or LED port address is not automatically updated; it must
be specifically updated to write data to a different address. During the sleep and standby modes, DDRAM,
CGRAM, or SEGRAM cannot be accessed.
1
RS R/W DB7
DB0
0
D
D
D
D
D
D
D
D
Figure 21 Write Data to RAM Instruction
Read Data from RAM
The read data from RAM instruction (Figure 22), reads 8-bit data from DDRAM, or 5-bit data from
CGRAM or SEGRAM that is selected by the previous specification of the address set instruction
(SEGRAM address set, CGRAM address set, or DDRAM address set). The unused upper three bits of
CGRAM or SEGRAM data are read as 000; annunciator data cannot be read. If no address is specified by
the address set instruction just before this instruction, the first data read will be invalid. When executing
consecutive read instructions, the next data is normally read from the next address.
相關PDF資料
PDF描述
HD66728 112 x 80-dot Graphics LCD Controller/Driver(112 x 80點圖形LCD控制器)
HD66730 Dot-Matrix Liquid Crystal Display Controller/Driver(點陣液晶顯示控制器/驅(qū)動器)
HD66731 Dot-Matrix Liquid Crystal Display Controller/Driver(點陣液晶顯示控制器/驅(qū)動器)
HD66731A00TB0L 122 x 32 pixel format, Compact LCD size
HD66731A00TA0L Dot-Matrix Liquid Crystal Display Controller/Driver Supporting Japanese Kanji, Korean Font Display
相關代理商/技術參數(shù)
參數(shù)描述
HD66727A03 制造商:未知廠家 制造商全稱:未知廠家 功能描述:LCD Display Driver
HD66727A03BP 制造商:未知廠家 制造商全稱:未知廠家 功能描述:LCD Display Driver
HD66727A03TA0 制造商:未知廠家 制造商全稱:未知廠家 功能描述:LCD Display Driver
HD66727A03TA0L 制造商:HITACHI 制造商全稱:Hitachi Semiconductor 功能描述:Low-Power Dot-Matrix Liquid Crystal Display Controller/Driver with Key Scan Function
HD66727A04 制造商:未知廠家 制造商全稱:未知廠家 功能描述:LCD Display Driver