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參數(shù)資料
| 型號： | HD66727A04TA0L |
| 廠商： | Hitachi,Ltd. |
| 英文描述： | Low-Power Dot-Matrix Liquid Crystal Display Controller/Driver with Key Scan Function |
| 中文描述： | 低功耗點陣液晶顯示控制器/鍵掃描功能驅(qū)動程序 |
| 文件頁數(shù)： | 39/97頁 |
| 文件大?。?/td> | 513K |
| 代理商： | HD66727A04TA0L |
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HD66727
39
Table 20
CGRAM Addresses and Character Codes
Displayed Character
CGRAM Address
Character Codes
1st character
“00”H to “07”H
“00”H
2nd character
“08”H to “0F”H
“01”H
3rd character
“10”H to “17”H
“02”H
4th character
“18”H to “1F”H
“03”H
DDRAM Address Set
The DDRAM address set instruction (Figure 20) includes the A (ADD), IRE, and KF bits.
AAAAAAA:
Used for setting the DDRAM address into the address counter (AC). The DDRAM addresses
range from “00”H to “4B”H (60 addresses) (Table 21).
Once the DDRAM address is set, data in the DDRAM can be accessed consecutively since the address
counter is automatically incremented or decremented according to the I/D bit setting after each access.
Here, invalid addresses are automatically skipped. The DDRAM address cannot be set during the sleep or
standby mode.
0
RS R/W DB7
DB0
Upper bits
Lower bits
0
1
1
0
IRE KF1 KF0
A
A
0
0
1
1
1
A
A
A
A
A
Figure 20 DDRAM Address Set Instruction
Table 21
DDRAM Addresses and Invalid Addresses
Displayed Line
DDRAM Address
Invalid Addresses
1st line
“00”H to “0B”H
“0C”H to “0F”H
2nd line
“10”H to “1B”H
“1C”H to “1F”H
3rd line
“20”H to “2B”H
“2C”H to “2F”H
4th line
“30”H to “3B”H
“3C”H to “3F”H
5th line
“40”H to “4B”H
“4C”H and subsequent addresses
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