參數(shù)資料
型號: HD66732
廠商: Hitachi,Ltd.
英文描述: Graphics Liquid Crystal Display Controller/Driver Supporting JIS Level-1 and Level-2 Kanji ROM(圖形LCD控制器/驅(qū)動器)
中文描述: 圖形液晶顯示控制器/驅(qū)動器支持日標級- 1和第2級漢字光盤(圖形液晶顯示控制器/驅(qū)動器)
文件頁數(shù): 47/133頁
文件大?。?/td> 2608K
代理商: HD66732
HD66732
47
Table 29
CT Bits and Variable Resistor Value of Contrast Adjuster
CT Set Value
Variable
Resistor (VR)
CT Set Value
Variable
CT4
CT3 CT2
CT1 CT0
CT4 CT3
CT2 CT1
CT0 Resistor (VR)
0
0
0
0
0
3.2 x R
1
0
0
0
0
1.6 x R
0
0
0
0
1
3.1 x R
1
0
0
0
1
1.5 x R
0
0
0
1
0
3.0 x R
1
0
0
1
0
1.4 x R
0
0
0
1
1
2.9 x R
1
0
0
1
1
1.3 x R
0
0
1
0
0
2.8 x R
1
0
1
0
0
1.2 x R
0
0
1
0
1
2.7 x R
1
0
1
0
1
1.1 x R
0
0
1
1
0
2.6 x R
1
0
1
1
0
1.0 x R
0
0
1
1
1
2.5 x R
1
0
1
1
1
0.9 x R
0
1
0
0
0
2.4 x R
1
1
0
0
0
0.8 x R
0
1
0
0
1
2.3 x R
1
1
0
0
1
0.7 x R
0
1
0
1
0
2.2 x R
1
1
0
1
0
0.6 x R
0
1
0
1
1
2.1 x R
1
1
0
1
1
0.5 x R
0
1
1
0
0
2.0 x R
1
1
1
0
0
0.4 x R
0
1
1
0
1
1.9 x R
1
1
1
0
1
0.3 x R
0
1
1
1
0
1.8 x R
1
1
1
1
0
0.2 x R
0
1
1
1
1
1.7 x R
1
1
1
1
1
0.1 x R
Power Control (R5)
AMP:
When AMP = 1, each voltage follower for V1 to V5 pins and the booster are turned on. When AMP
= 0, current consumption can be reduced while the display is not being used.
BT1-0:
Switch the output of V5OUT between single, double, triple, and quadruple boost. The LCD drive
voltage level can be selected according to its drive duty ratio and bias. A lower amplification of the booster
consumes less current. When BT1/0 = "00", a single boost is output. When BT1/0 = "01", a double boost
is output. When BT1/0 = "10", a triple boost is output. When BT1/0 = "11", a quadruple boost is output.
SLP:
When SLP = 1, the HD66732 enters the sleep mode, where the internal operations are halted except
for the key scan function and the R-C oscillator, thus reducing current consumption. For details, see the
Sleep Mode section. Only the following instructions can be executed during the sleep mode.
a. Key scan data read
b. Key scan control (IRE, KF1/0 bit)
c. Power control (AMP, SLP, and STB bits)
d. Port control (PT2-0 bits)
During the sleep mode, the other RAM data and instructions cannot be updated although they are retained.
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