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參數(shù)資料
| 型號： | HD74HC165 |
| 廠商： | Hitachi,Ltd. |
| 英文描述： | Octal Buffers/Drivers With 3-State Outputs 20-LCCC -55 to 125 |
| 中文描述： | 并聯(lián)負載8位的移位寄存器 |
| 文件頁數(shù)： | 1/9頁 |
| 文件大小： | 47K |
| 代理商： | HD74HC165 |
HD74HC165
Parallel-load 8-bit Shift Register
Description
This 8-bit serial shift register shifts data from Q
A
to Q
H
when clocked. Parallel inputs to each stage are
enabled by a low level at the Shift/Load input. Also included is a gated clock input and a complementary
output from the eighth bit.
Clocking is accomplished through a 2-input NOR gate permitting one input to be used as a clock inhibit
function. Holding either of the clock inputs high inhibits clocking, and holding either clock input low with
the Shift/Load input high enables the other clock input. Data transfer occurs on the positive going edge of
the clock. Parallel loading is inhibited as long as the Shift/Load input is high. When taken low, data at the
parallel inputs is loaded directly into the register independent of the state of the clock.
Features
High Speed Operation: t
pd
(Clock to Q
H
) = 21 ns typ (C
L
= 50 pF)
High Output Current: Fanout of 10 LSTTL Loads
Wide Operating Voltage: V
CC
= 2 to 6 V
Low Input Current: 1 μA max
Low Quiescent Supply Current: I
CC
(static) = 4 μA max (Ta = 25°C)
Function Table
Inputs
Parallel
Internal outputs
Output
Shift/Load
Clock Inhibit
Clock
Serial
A ······ H
Q
A
a
Q
B
b
Q
H
h
L
X
X
X
a ······h
H
L
L
X
X
Q
A0
H
Q
B0
Q
An
Q
H0
Q
Gn
H
L
H
X
H
L
L
X
L
Q
An
Q
Gn
H
H
X
X
X
Q
A0
Q
B0
Q
H0
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