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參數(shù)資料
| 型號： | HD74HC195 |
| 廠商： | Hitachi,Ltd. |
| 英文描述： | 4-bit Parallel-Access Shift Register |
| 中文描述： | 4位并行存取移位寄存器 |
| 文件頁數(shù)： | 2/9頁 |
| 文件大小： | 50K |
| 代理商： | HD74HC195 |
HD74HC195
2
Function Table
Inputs
Shift/
Serial
Parallel
Outputs
Clear Load Clock J
K
A
B
C
D
Q
A
L
Q
B
L
Q
C
L
Q
D
L
Q
D
H
d
L
X
X
X
X
X
X
X
X
H
L
X
X
a
b
c
d
a
b
c
d
H
H
L
X
X
X
X
X
X
Q
A0
Q
A0
Q
B0
Q
A0
Q
C0
Q
Bn
Q
D0
Q
Cn
Q
D0
Q
Cn
Q
Cn
Q
Cn
Q
Cn
H
H
L
H
X
X
X
X
H
H
L
L
X
X
X
X
L
Q
An
Q
Bn
Q
Cn
H
H
H
H
X
X
X
X
H
Q
An
Q
Bn
Q
Cn
H
H
H
L
X
X
X
X
Q
An
Q
An
Q
Bn
Q
Cn
H :
L
X :
high level (steady state)
low level (steady state)
don’t care
:
transition from low to high level.
a, b, c, d
:
the level of steady-state input at inputs A, B, C or D respectively.
Q
A0
, Q
B0
, Q
C0
, Q
D0
:
the level of Q
, Q
, Q
or Q
D
respectively, before the indicated steady-state input
conditions were established.
Q
An
, Q
Bn
, Q
Cn
, Q
Dn
:
the level of Q
A
, Q
B
, Q
C
or Q
D
respectively before the most recent
the clock.
:
transition of
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