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參數(shù)資料
| 型號： | HD74LV163A |
| 廠商： | Hitachi,Ltd. |
| 元件分類： | 通用總線功能 |
| 英文描述： | Synchronous 4-bit Binary Counter (Synchronous Clear) |
| 中文描述： | 同步4位二進(jìn)制計(jì)數(shù)器（同步清除） |
| 文件頁數(shù)： | 8/19頁 |
| 文件大?。?/td> | 77K |
| 代理商： | HD74LV163A |
HD74LV163A
8
Switching Characteristics
V
CC
= 2.5
±
0.2 V
Ta = 25
°
C
Ta = –40 to 85
°
C
Item
Symbol
Min
Typ
Max
Min
Max
Unit
Test Conditions
FROM
(Input)
TO
(Output)
Maximum
clock
frequency
fmax
50
90
—
40
—
MHz
C
L
= 15 pF
30
60
—
25
—
C
L
= 50 pF
Propa-
gation
delay time
t
PLH
/t
PHL
—
11.1
16.2
1.0
19.5
ns
C
L
= 15 pF
CLK
Q
—
14.3
19.2
1.0
22.5
C
L
= 50 pF
t
PLH
/t
PHL
—
11.5
17.0
1.0
20.5
C
L
= 15 pF
CLK
Carry
Count
mode
—
14.7
20.0
1.0
23.5
C
L
= 50 pF
t
PLH
/t
PHL
L
oad
mode
—
13.8
20.6
1.0
24.5
C
L
= 15 pF
CLK
Carry
—
17.0
23.6
1.0
27.5
C
L
= 50 pF
t
PLH
/t
PHL
—
10.3
15.7
1.0
19.0
C
L
= 15 pF
ENT
Carry
—
14.0
18.7
1.0
22.0
C
L
= 50 pF
Setup time
t
su
7.5
—
—
8.5
—
ns
Data before CLK
↑
10.0
—
—
11.5
—
LOAD
before CLK
↑
9.5
—
—
11.0
—
ENT, ENP before
CLK
↑
6.0
—
—
6.0
—
CLR
before CLK
↑
Hold time
t
h
1.5
—
—
1.5
—
ns
1.5
—
—
1.5
—
CLR
after CLK
↑
Pulse
width
t
w
7.0
—
—
7.0
—
ns
CLK H or L
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