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參數(shù)資料
| 型號(hào)： | HD74LVC16373A |
| 廠商： | Hitachi,Ltd. |
| 英文描述： | 9-Channel Differential Transceiver 56-SSOP |
| 中文描述： | 16位D型透明鎖存器與三態(tài)輸出 |
| 文件頁(yè)數(shù)： | 1/10頁(yè) |
| 文件大?。?/td> | 56K |
| 代理商： | HD74LVC16373A |
HD74LVC16373A
16-bit D-type Transparent Latches with 3-state Outputs
ADE-205-121B(Z)
3rd Edition
December 1996
Description
The HD74LVC16373A has sixteen D type latches with three state outputs in a 48 pin package. When the
latch enable input is high, the Q outputs will follow the D inputs. When the latch enable goes low, data at
the D inputs will be retained at the outputs until latch enable returns high again. When a high logic level is
applied to the output control input (1
G
, 2
G
), all outputs go to a high impedance state, regardless of what
signals are present at the other inputs and the state of the storage elements. Low voltage and high speed
operation is suitable at the battery drive product (note type personal computer) and low power consumption
extends the life of a battery for long time operation.
Features
V
CC
= 2.0 V to 5.5 V
All inputs V
IH
(Max.) = 5.5 V (@V
CC
= 0 V to 5.5 V)
All outputs V
OUT
(Max.) = 5.5 V (@V
CC
= 0 V or output off state)
Typical V
OL
ground bounce < 0.8 V (@V
CC
= 3.3 V, Ta = 25°C)
Typical V
OH
undershoot > 2.0 V (@V
CC
= 3.3 V, Ta = 25°C)
High output current ±24 mA (@V
CC
= 3.0 V to 5.5 V)
Function Table
Inputs
G
LE
D
Output Q
H
X
X
Z
L
H
L
L
L
H
H
H
L
H:
L:
X:
Z:
Q
0
:
L
X
Q
0
High level
Low level
Immaterial
High impedance
Level of Q before the indicated steady input conditions were established.
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