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參數(shù)資料
| 型號： | HDM8513AP |
| 廠商： | Hynix Semiconductor Inc. |
| 英文描述： | Timer IC; Supply Voltage Max:16V; Package/Case:14-DIP; Current Rating:10A; Timer Type:Timer-Dual; Mounting Type:Through Hole |
| 中文描述： | 的DVB /決策支持系統(tǒng)兼容接收器 |
| 文件頁數(shù)： | 24/67頁 |
| 文件大?。?/td> | 261K |
| 代理商： | HDM8513AP |
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24
3.4 Viterbi Decoder
The Viterbi decoder accepts 3 bit soft decision samples of the in-phase (I) and quadrature (Q)
components of the received signal. Once QPSK lock has been achieved, the decoder searches for
the correct code rate, starting with rate 3/4, then proceeding to rate 2/3, 5/6, 7/8 and finally rate
1/2. Each of the possible synchronization phases at each rate is tested as well as the two
possible carrier phase ambiguity conditions. Polarity reversal is corrected in the word
synchronization logic. Viterbi lock is achieved when the trellis traceback algorithm converges, on
the average, within a prescribed number of symbols.
Although the algorithm automatically tests for carrier phase ambiguity, there is no provision to
automatically correct for phase reversal. Phase reversal can occur if the receiver chain, consisting
of an LNB and the tuner, provides an odd number of high side frequency translation operations. A
system may be required to operate with different LNBs, some of which provide phase reversal.
This condition may be corrected by the host processor, which can set a bit in the down converter
to correct for phase reversal.
The Viterbi decoder employs the radix two algorithm. The output buffer reserializes the data which
is made available, along with the Viterbi data clock as external signals. These signals permit
verification of the DVB specification which is referenced to the Viterbi decoder output.
ACS Array
Trace-back
RAM
Traceback Memory
Controller
Decoder
Quality
Estimate
Last-In
First-Out
Buffer
Data
Out
Viterbi
Lock
Clock
Out
Depuncturing
Logic
Branch Metric
Calculator
Change Puncture Phase
Change Carrier Phase
I
Q
G1
G2
3
3
128
F
IGURE
18: V
ITERBI
D
ECODER
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