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King Billion Electronics Co., Ltd
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億
電
子
股
份
有
限
公
司
HE847701
HE80000 SERIES
March 26, 2004
This specification is subject to change without notice. Please contact sales person for the latest version before use.
Page 4 of 29
V1.03
Pin Name
Pin # I/O
Description
will turn on the key scan function.
8-bit bi-directional I/O port 14 is shared with LCD segment pads SEG[23..16]. The
function of the pad can be selected individually by mask options MO_LIO14[7..0].
(‘1’ for LCD and ‘0’ for I/O).
The output type of I/O pad can also be selected by mask option MO_14PP[7..0] (1
for push-pull and ‘0’ for open-drain).
As the output structure of I/O pad does not contain tri-state buffer. When using the
I/O as input, “1” must be outputted before reading.
8-bit bi-directional I/O port 15 is shared with LCD segment pads SEG[16..8]. The
function of the pad can be selected individually by mask options MO_LIO15[7..0].
(‘1’ for LCD and ‘0’ for I/O).
The output type of I/O pad can also be selected by mask option MO_15PP[7..0] (1
for push-pull and ‘0’ for open-drain).
As the output structure of I/O pad does not contain tri-state buffer. When using the
I/O as input, “1” must be outputted before reading.
8-bit bi-directional I/O port 17 is shared with LCD segment pads SEG[7..0]. The
function of the pad can be selected individually by mask options MO_LIO17[7..0].
(‘1’ for LCD and ‘0’ for I/O).
The output type of I/O pad can also be selected by mask option MO_17PP[7..0] (1
for push-pull and ‘0’ for open-drain).
As the output structure of I/O pad does not contain tri-state buffer. When using the
I/O as input, “1” must be outputted before reading.
50 ~ 81 O LCD COMMON Driver pads.
82
B LCD Bias Voltage 1
83
B LCD Bias Voltage 2
84
B LCD Bias Voltage 3
85
B LCD Bias Voltage 4
86
B LCD Bias Voltage 5
87
B Charge Pump Capacitor Pin
88
B
Charge Pump Capacitor Pin.
89
B Charge Pump Capacitor Pin
90
B Charge Pump Capacitor Pin
91
B Charge Pump Capacitor Pin
92
B Charge Pump Capacitor Pin
93
B
Charge Pump Capacitor Pin
94
B
Charge Pump Capacitor Pin
95
B LCD Voltage setting. Adjust Resistor between LCDGS and LVL2 to set LVL5.
96
B Charge Pump Capacitor Pin
97
B
Charge Pump Capacitor Pin
98
O
LCD frame signal for interfacing with LCD segment extender KD80.
99
O
LCD data load pin for interfacing with LCD segment extender KD80.
100
P
Power ground Input.
DAC Voice Output. Set the bit 1 and clear the bit 0 of VOC (DA = ‘1’ and OP = ‘0’)
register to turn on DAC with VO output.
Alternate output of DAC. Set both bit 1 and bit 0 of VOC register (DA = ‘1’ and OP
= ‘1’) to turn on DAC with DAO output as well as OP comparator.
Inverting input of OP Amp. Set the bit 0 of VOC register (OP = ‘1’) to turn on OP
comparator.
104
I
Non-inverting input of OP Amp.
105
O Output of OP Amp.
System Reset input pin. Level trigger, active low on this pin will put the chip in reset
state.
PRT14[7..0]
26 ~ 33 B/
O
PRT15[7..0]
34 ~ 41 B/
O
PRT17[7..0]
42 ~ 49 B/
O
COM[31..0]
LVL1
LVL2
LVL3
LVL4
LVL5
LCAP4A
LCAP4B
LCAP3A
LCAP3B
LCAP2A
LCAP2B
LCAP1A
LCAP1B
LCDGS
LCDVX
LCDVTB
LFR
LDL
GND
VO
101
O
DAO
102
O
OPIN
103
I
OPIP
OPO
RSTP_N
106
I