參數(shù)資料
型號: HEC4013BT,118
廠商: NXP Semiconductors
文件頁數(shù): 15/16頁
文件大小: 0K
描述: IC FLIP FLOP DUAL D TYPE 14-SOIC
產(chǎn)品培訓(xùn)模塊: Logic Packages
標(biāo)準(zhǔn)包裝: 2,500
系列: 4000B
功能: 設(shè)置(預(yù)設(shè))和復(fù)位
類型: D 型
輸出類型: 差分
元件數(shù): 2
每個元件的位元數(shù): 1
頻率 - 時鐘: 40MHz
觸發(fā)器類型: 正邊沿
輸出電流高,低: 3.4mA,3.4mA
電源電壓: 3 V ~ 15 V
工作溫度: -40°C ~ 125°C
安裝類型: 表面貼裝
封裝/外殼: 14-SOIC(0.154",3.90mm 寬)
包裝: 帶卷 (TR)
HEF4013B
All information provided in this document is subject to legal disclaimers.
NXP B.V. 2011. All rights reserved.
Product data sheet
Rev. 8 — 21 November 2011
8 of 16
NXP Semiconductors
HEF4013B
Dual D-type flip-flop
Recovery times are shown as positive values but may be specified as negative values.
Measurement points are given in Table 9.
Fig 5.
nSD, nCD recovery time and pulse width
001aag088
input nSD
input nCD
input nCP
VI
0 V
VOL
0 V
VI
VOH
tW
VM
tW
VM
output nQ
trec
Table 9.
Measurement points
Supply voltage
Input
Output
VDD
VM
VX
VY
5 V to 15 V
0.5VDD
0.1VDD
0.9VDD
Test and measurement data is given in Table 10;
Definitions test circuit:
DUT = Device Under Test.
RT = Termination resistance should be equal to output impedance Zo of the pulse generator.
CL = Load capacitance including jig and probe capacitance.
Fig 6.
Test circuit for measuring switching times
VDD
VI
VO
001aag182
DUT
CL
RT
G
Table 10.
Test data
Supply voltage
Input
Load
VDD
VI
tr, tf
CL
5 V to 15 V
VSS or VDD
20 ns
50 pF
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