參數(shù)資料
型號(hào): HEF4015BT
廠商: NXP Semiconductors N.V.
元件分類: 通用總線功能
英文描述: Dual 4-bit static shift register
封裝: HEF4015BP<SOT38-4 (DIP16)|<<http://www.nxp.com/packages/SOT38-4.html<1<Always Pb-free,;HEF4015BT<SOT109-1 (SO16)|<<http://www.nxp.com/packages/SOT109-1.html<1<week
文件頁(yè)數(shù): 3/15頁(yè)
文件大小: 144K
代理商: HEF4015BT
HEF4015B
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NXP B.V. 2011. All rights reserved.
Product data sheet
Rev. 7 — 14 September 2011
3 of 15
NXP Semiconductors
HEF4015B
Dual 4-bit static shift register
6. Pinning information
6.1 Pinning
6.2 Pin description
7. Functional description
[1]
H = HIGH voltage level; L = LOW voltage level; X = don’t care; Dn = either HIGH or LOW;
= positive-going transition;
= negative-going transition.
Fig 3.
Pin configuration
HEF4015B
2CP
V
DD
2Q3
2D
1Q2
2MR
1Q1
2Q0
1Q0
2Q1
1MR
2Q2
1D
1Q3
V
SS
1CP
001aae561
1
2
3
4
5
6
7
8
10
9
12
11
14
13
16
15
Table 2.
Symbol
1Q0 to 1Q3
2Q0 to 2Q3;
1MR, 2MR
1D, 2D
V
SS
1CP, 2CP
V
DD
Pin description
Pin
5, 4, 3, 10
13, 12, 11, 2
6, 14
7, 15
8
9, 1
16
Description
parallel output
parallel output
master reset input (active HIGH)
serial data input
ground supply voltage
clock input (LOW-to-HIGH edge-triggered)
supply voltage
Table 3.
number of clock
pulse transitions
Function table
[1]
Input
CP
X
Output
Q0
D1
D2
D3
D4
no change
L
D
D1
D2
D3
D4
X
X
MR
L
L
L
L
L
H
Q1
X
D1
D2
D3
no change
L
Q2
X
X
D1
D2
no change
L
Q3
X
X
X
D1
no change
L
1
2
3
4
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