參數(shù)資料
型號(hào): HEF4093BT
廠商: NXP Semiconductors N.V.
元件分類: 通用總線功能
英文描述: Quad 2-input NAND Schmitt trigger
中文描述: 四2輸入與非施密特觸發(fā)器
封裝: HEC4093BT<SOT108-1 (SO14)|<<http://www.nxp.com/packages/SOT108-1.html<1<week 32, 2004,;HEC4093BT<SOT108-1 (SO14)|<<http://www.nxp.com/packages/SOT108-1.html<1<week
文件頁數(shù): 6/15頁
文件大?。?/td> 367K
代理商: HEF4093BT
HEF4093B
All information provided in this document is subject to legal disclaimers.
NXP B.V. 2010. All rights reserved.
Product data sheet
Rev. 7 — 1 September 2010
6 of 15
NXP Semiconductors
HEF4093B
Quad 2-input NAND Schmitt trigger
12. Waveforms
Table 9.
Supply voltage
V
DD
5 V to 15 V
Table 10.
Supply voltage
V
DD
5 V to 15 V
Measurement points are given in
Table 9
.
Logic levels: V
OL
and V
OH
are typical output voltage levels that occur with the output load.
t
r
, t
f
= input rise and fall times.
Propagation delay and output transition time
Fig 4.
001aag197
input
output
t
PLH
t
PHL
0 V
V
I
V
M
10 %
V
M
V
OH
V
OL
t
TLH
t
THL
90 %
10 %
90 %
t
r
t
f
Measurement points
Input
V
M
0.5V
DD
Output
V
M
0.5V
DD
Test data given in
Table 10
.
Definitions for test circuit:
DUT = Device Under Test.
C
L
= load capacitance including jig and probe capacitance.
R
T
= termination resistance should be equal to the output impedance Z
o
of the pulse generator.
Test circuit
Fig 5.
V
DD
V
I
V
O
001aag182
DUT
CL
RT
G
Test data
Input
V
I
V
SS
or V
DD
Load
C
L
50 pF
t
r
, t
f
20 ns
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