參數(shù)資料
型號: HEF4518BF
廠商: NXP Semiconductors N.V.
元件分類: 通用總線功能
英文描述: Dual BCD counter
中文描述: 雙BCD碼計(jì)數(shù)器
文件頁數(shù): 2/7頁
文件大?。?/td> 66K
代理商: HEF4518BF
January 1995
2
Philips Semiconductors
Product specification
Dual BCD counter
HEF4518B
MSI
DESCRIPTION
T he HEF4518B is a dual 4-bit internally synchronous BCD
counter. The counter has an active HIGH clock input
(CP
0
) and an active LOW clock input (CP
1
), buffered
outputs from all four bit positions (O
0
to O
3
) and an active
HIGH overriding asynchronous master reset input (MR).
The counter advances on either the LOW to HIGH
transition of the CP
0
input if CP
1
is HIGH or the HIGH to
LOW transition of the CP
1
input if CP
0
is LOW. Either CP
0
or CP
1
may be used as the clock input to the counter and
the other clock input may be used as a clock enable input.
A HIGH on MR resets the counter (O
0
to O
3
= LOW)
independent of CP
0
, CP
1
.
Schmitt-trigger action in the clock input makes the circuit
highly tolerant to slower clock rise and fall times.
Fig.1 Functional diagram.
HEF4518BP(N):
HEF4518BD(F):
HEF4518BT(D):
( ): Package Designator North America
16-lead DIL; plastic (SOT38-1)
16-lead DIL; ceramic (cerdip) (SOT74)
16-lead SO; plastic (SOT109-1)
Fig.2 Pinning diagram.
PINNING
CP
0A
, CP
0B
CP
1A
, CP
1B
MR
A
, MR
B
O
0A
to O
3A
O
0B
to O
3B
clock inputs (L to H triggered)
clock inputs (H to L triggered)
master reset inputs
outputs
outputs
APPLICATION INFORMATION
Some examples of applications for the HEF4518B are:
Multistage synchronous counting.
Multistage asynchronous counting.
Frequency dividers.
FAMILY DATA, I
DD
LIMITS category MSI
See Family Specifications
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