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參數(shù)資料
| 型號： | HEF4526B |
| 廠商： | NXP Semiconductors N.V. |
| 元件分類： | 通用總線功能 |
| 英文描述： | Programmable 4-bit binary down counter(可編程4位二進制減法計數(shù)器) |
| 中文描述： | 可編程4位二進制減計數(shù)器（可編程4位二進制減法計數(shù)器） |
| 文件頁數(shù)： | 2/10頁 |
| 文件大小： | 109K |
| 代理商： | HEF4526B |
January 1995
2
Philips Semiconductors
Product specification
Programmable 4-bit binary down counter
HEF4526B
MSI
DESCRIPTION
The HEF4526B is a synchronous programmable 4-bit
binary down counter with an active HIGH and an active
LOW clock input (CP
0
, CP
1
), an asynchronous parallel
load input (PL), four parallel inputs (P
0
to P
3
), a cascade
feedback input (CF), four buffered parallel outputs (O
0
to
O
3
), a terminal count output (TC) and an overriding
asynchronous master reset input (MR).
This device is a programmable, cascadable down counter
with a decoded TC output for divide-by-n applications. In
single stage applications the TC output is connected to PL.
CF allows cascade divide-by-n operation with no
additional gates required.
Information on P
0
to P
3
is loaded into the counter while PL
is HIGH, independent of all other input conditions except
MR, which must be LOW. When PL and CP
1
are LOW, the
counter advances on a LOW to HIGH transition of CP
0
.
When PL is LOW and CP
0
is HIGH, the counter advances
on a HIGH to LOW transition of CP
1
. TC is HIGH when the
counter is in the zero state (O
0
= O
1
= O
2
= O
3
= LOW)
and CF is HIGH and PL is LOW. A HIGH on MR resets the
counter (O
0
to O
3
= LOW) independent of other input
conditions.
Schmitt-trigger action in the clock input makes the circuit
highly tolerant to slower clock rise and fall times.
FAMILY DATA, I
DD
LIMITS category MSI
See Family Specifications
Fig.1 Functional diagram.
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