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參數(shù)資料
| 型號(hào)： | HEF4738V |
| 廠商： | NXP Semiconductors N.V. |
| 英文描述： | IEC/IEEE bus interface |
| 中文描述： | 東區(qū)走廊/電機(jī)及電子學(xué)工程師聯(lián)合會(huì)總線接口 |
| 文件頁數(shù)： | 4/8頁 |
| 文件大?。?/td> | 118K |
| 代理商： | HEF4738V |
January 1995
4
Philips Semiconductors
Product specification
IEC/IEEE bus interface
HEF4738V
LSI
Note
After power-on the input Ipon must stay LOW for at least
32 clock pulses, then HIGH for 32 clock pulses in order to
force the function to its initial state.
After this, Ipon must be set LOW.
HEF4738VP(N):
( ): Package Designator North America
40-lead DIL; plastic (SOT129-1)
Fig.2
Pinning diagram; for abbreviations see the
following list.
Input pins
Output pins
Supply pins
Note
1.
Isr is serial input for signals A5, A4, A3, A2, A1, ton,
Ion, lt, rsv, rtl and ist.
1,2,3,36,
37, 38, 39
4 = IIDY
9 = Isr (note 1)
11 = IIFC
12 = Ipon
13 = IDAV
14 = Irdy
18 = IATN
24 = IRFD
25 = Inba
26 = IDAC
27 = lcats
28 = IREN
31 = CP
= ID101 to 7:
input DIO
input IDY not
input shift register
input IFC not
input pon
input DAV not
input rdy not
input ATN not
input RFD
input nba not
input DAC
inputs cats
input REN not
clock pulse input
5 = OPP
8,7,6, = OP1 to OP3
10 = Ored
15 = ORFD
16 = ODAC
17 = Odvd
19 = OSRQ
21 = ORQS
22 = Odcd
23 = ODAV
29 = Osp
30 = Ota
32 = Oloc
33 = Oclr
34 = Otct
35 = Otrg
output PP
output P1 to P3
output red
output RFD
output DAC
output dvd
output SRQ not
output RQS not
output dcd
output DAV not
output sp
output ta
output loc
output clr
output tct
output trg
20 = V
SS
:
40 = V
DD
:
more negative supply line
more positive supply line
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