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參數資料
| 型號： | HFA1113883 |
| 廠商： | Intersil Corporation |
| 英文描述： | CAP .1UF 200V B SERIES POLY |
| 中文描述： | 輸出限制，超高速可編程增益緩沖放大器 |
| 文件頁數： | 19/22頁 |
| 文件大?。?/td> | 568K |
| 代理商： | HFA1113883 |
DESIGN INFORMATION
(Continued)
The information contained in this section has been developed through characterization by Intersil Semiconductor and is for use as
application and design information only. No guarantee is implied.
207
HFA1113
Clamp Operation
General
The HFA1113 features user programmable output clamps to
limit output voltage excursions. Clamping action is obtained
by applying voltages to the V
H
and V
L
terminals (DIP pins 8
& 5) of the amplifier. V
H
sets the upper output limit, while V
L
sets the lower clamp level. If the amplifier tries to drive the
output above V
H
, or below V
L
, the clamp circuitry limits the
output voltage at V
H
or V
L
(
±
the clamp accuracy), respec-
tively. The low input bias currents of the clamp pins allow
them to be driven by simple resistive divider circuits, or
active elements such as amplifiers or DACs.
Clamp Circuitry
Figure 3 shows a simplified schematic of the HFA1113 input
stage, and the high clamp (V
H
) circuitry. As with all current
feedback amplifiers, there is a unity gain buffer (QX1 - QX2)
between the positive and negative inputs. This buffer forces
-IN to track +IN, and sets up a slewing current of:
(V
-IN
- V
OUT
)/R
F
+ V
-IN
/ R
G
.
This current is mirrored onto the high impedance node (Z) by
QX3-QX4, where it is converted to a voltage and fed to the
output via another unity gain buffer. If no clamping is utilized,
the high impedance node may swing within the limits defined
by QP4 and QN4. Note that when the output reaches it’s qui-
escent value, the current flowing through -IN is reduced to
only that small current (-I
BIAS
) required to keep the output at
the final voltage.
Tracing the path from V
H
to Z illustrates the effect of the
clamp voltage on the high impedance node. V
H
decreases
by 2V
BE
(QN6 and QP6) to set up the base voltage on QP5.
QP5 begins to conduct whenever the high impedance node
reaches a voltage equal to QP5’s base voltage + 2V
BE
(QP5
and QN5). Thus, QP5 clamps node Z whenever Z reaches
V
H
. R1 provides a pull-up network to ensure functionality
with the clamp inputs floating. A similar description applies to
the symmetrical low clamp circuitry controlled by V
L
.
When the output is clamped, the negative input continues to
source a slewing current (I
CLAMP
) in an attempt to force the
output to the quiescent voltage defined by the input. QP5
must sink this current while clamping, because the -IN cur-
rent is always mirrored onto the high impedance node. The
clamping current is calculated as:
I
CLAMP
= (V
-IN
- V
OUT CLAMPED
) / 300
+ V
-IN
/ R
G
.
As an example, a unity gain circuit with V
IN
= 2V, and V
H
=
1V, would have I
CLAMP
= (2V-1V) / 300
+ 2V /
∞
= 3.33mA
(R
G
=
∞
because -IN is floated for unity gain applications).
Note that I
CC
will increase by I
CLAMP
when the output is
clamp limited.
Clamp Accuracy
The clamped output voltage will not be exactly equal to the
voltage applied to V
H
or V
L
. Offset errors, mostly due to V
BE
mismatches, necessitate a clamp accuracy parameter which
is found in the device specifications. Clamp accuracy is a
function of the clamping conditions. Referring again to Figure
3, it can be seen that one component of clamp accuracy is the
V
BE
mismatch between the QX6 transistors, and the QX5
transistors. If the transistors always ran at the same current
level there would be no V
BE
mismatch, and no contribution to
the inaccuracy. The QX6 transistors are biased at a constant
current, but as described earlier, the current through QX5 is
equivalent to I
CLAMP
. V
BE
increases as I
CLAMP
increases,
FIGURE 2. EVALUATION BOARD SCHEMATIC AND LAYOUT
FIGURE 3. HFA1113 SIMPLIFIED V
H
CLAMP CIRCUITRY
V
H
+IN
V
L
V+
GND
1
V-
OUT
BOTTOM LAYOUT
TOP LAYOUT
1
2
3
4
8
7
6
5
+5V
10
μ
F
0.1
μ
F
V
H
50
GND
GND
R1
-5V
0.1
μ
F
10
μ
F
50
IN
OUT
V
L
∞
(A
V
= +1)
or 0
(A
V
= +2)
+1
+IN
V-
V+
QP1
QN1
V-
QN3
QP3
QP4
QN2
QP2
QN4QP5
QN5
Z
V+
-IN
V
OUT
I
CLAMP
R
F
= 300
(INTERNAL)
QP6
QN6
V
H
R1
50K
(30K
FOR
V
L
)
300
V
-IN
R
G
(INTERNAL)
200
Spec Number
511106-883
相關PDF資料 |
PDF描述 |
|---|---|
| HFA1113IB | Hook-Up Wire; Conductor Size AWG:30; No. Strands x Strand Size:Solid; Jacket Color:Purple; Approval Bodies:UL, CSA; Approval Categories:UL AWM Style 1061; CSA AWM; Conductor Material:Copper; Jacket Material:Polyvinylchloride (PVC) RoHS Compliant: Yes |
| HFA1113EVAL | 850MHz, Low Distortion, Output Limiting, Programmable Gain, Buffer Amplifier |
| HFA1114IB | 850MHz Video Cable Driving Buffer |
| HFA1114IP | 850MHz Video Cable Driving Buffer |
| HFA1114 | 850MHz Video Cable Driving Buffer(850MHz、視頻電纜驅動緩沖器) |
相關代理商/技術參數 |
參數描述 |
|---|---|
| HFA1113EVAL | 制造商:INTERSIL 制造商全稱:Intersil Corporation 功能描述:850MHz, Low Distortion, Output Limiting, Programmable Gain, Buffer Amplifier |
| HFA1113IB | 功能描述:IC BUFFER 850MHZ 8-SOIC RoHS:否 類別:集成電路 (IC) >> Linear - Amplifiers - Instrumentation 系列:- 標準包裝:50 系列:LinCMOS™ 放大器類型:通用 電路數:4 輸出類型:- 轉換速率:0.05 V/µs 增益帶寬積:110kHz -3db帶寬:- 電流 - 輸入偏壓:0.7pA 電壓 - 輸入偏移:210µV 電流 - 電源:57µA 電流 - 輸出 / 通道:30mA 電壓 - 電源，單路/雙路(±):3 V ~ 16 V，±1.5 V ~ 8 V 工作溫度:-40°C ~ 85°C 安裝類型:表面貼裝 封裝/外殼:14-SOIC（0.154"，3.90mm 寬） 供應商設備封裝:14-SOIC 包裝:管件 產品目錄頁面:865 (CN2011-ZH PDF) 其它名稱:296-1834296-1834-5 |
| HFA1113IBZ | 功能描述:運算放大器 - 運放 W/ANNEAL BUFR 850MHZ CFB PRG-GAIN CLMP RoHS:否 制造商:STMicroelectronics 通道數量:4 共模抑制比（最小值）:63 dB 輸入補償電壓:1 mV 輸入偏流（最大值）:10 pA 工作電源電壓:2.7 V to 5.5 V 安裝風格:SMD/SMT 封裝 / 箱體:QFN-16 轉換速度:0.89 V/us 關閉:No 輸出電流:55 mA 最大工作溫度:+ 125 C 封裝:Reel |
| HFA1113IBZ96 | 功能描述:運算放大器 - 運放 W/ANNEAL BUFR 850MHZ CFB PRG-GAIN CLMP RoHS:否 制造商:STMicroelectronics 通道數量:4 共模抑制比（最小值）:63 dB 輸入補償電壓:1 mV 輸入偏流（最大值）:10 pA 工作電源電壓:2.7 V to 5.5 V 安裝風格:SMD/SMT 封裝 / 箱體:QFN-16 轉換速度:0.89 V/us 關閉:No 輸出電流:55 mA 最大工作溫度:+ 125 C 封裝:Reel |
| HFA1113IP | 制造商:Rochester Electronics LLC 功能描述:- Bulk |
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