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參數(shù)資料
| 型號： | HFA1113IBZ96 |
| 廠商： | Intersil |
| 文件頁數(shù)： | 13/16頁 |
| 文件大?。?/td> | 0K |
| 描述： | IC BUFFER 850MHZ 8-SOIC |
| 標(biāo)準(zhǔn)包裝： | 2,500 |
| 放大器類型： | 緩沖器 |
| 電路數(shù)： | 1 |
| 轉(zhuǎn)換速率： | 2400 V/µs |
| -3db帶寬： | 850MHz |
| 電流 - 輸入偏壓： | 25µA |
| 電壓 - 輸入偏移： | 8000µV |
| 電流 - 電源： | 21mA |
| 電流 - 輸出 / 通道： | 60mA |
| 電壓 - 電源，單路/雙路(±)： | 9 V ~ 11 V，±4.5 V ~ 5.5 V |
| 工作溫度： | -40°C ~ 85°C |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 8-SOIC（0.154"，3.90mm 寬） |
| 供應(yīng)商設(shè)備封裝： | 8-SOIC |
| 包裝： | 帶卷 (TR) |
6
FN1342.6
July 11, 2005
.
Limiting Operation
General
The HFA1113 features user programmable output clamps to
limit output voltage excursions. Clamping action is obtained
by applying voltages to the VH and VL terminals (pins 8 and
5) of the amplifier. VH sets the upper output limit, while VL
sets the lower clamp level. If the amplifier tries to drive the
output above VH, or below VL, the clamp circuitry limits the
output voltage at VH or VL (± the clamp accuracy),
respectively. The low input bias currents of the clamp pins
allow them to be driven by simple resistive divider circuits, or
active elements such as amplifiers or DACs.
Clamp Circuitry
Figure 4 shows a simplified schematic of the HFA1113 input
stage, and the high clamp (VH) circuitry. As with all current
feedback amplifiers, there is a unity gain buffer (QX1 - QX2)
between the positive and negative inputs. This buffer forces
-IN to track +IN, and sets up a slewing current of:
(V-IN - VOUT)/RF + V-IN/RG
This current is mirrored onto the high impedance node (Z) by
QX3-QX4, where it is converted to a voltage and fed to the
output via another unity gain buffer. If no clamping is utilized,
the high impedance node may swing within the limits defined
by QP4 and QN4. Note that when the output reaches its
quiescent value, the current flowing through -IN is reduced to
only that small current (-IBIAS) required to keep the output at
the final voltage.
Tracing the path from VH to Z illustrates the effect of the
clamp voltage on the high impedance node. VH decreases
by 2VBE (QN6 and QP6) to set up the base voltage on QP5.
QP5 begins to conduct whenever the high impedance node
reaches a voltage equal to QP5’s base voltage + 2VBE (QP5
and QN5). Thus, QP5 clamps node Z whenever Z reaches
VH. R1 provides a pull-up network to ensure functionality
with the clamp inputs floating. A similar description applies to
the symmetrical low clamp circuitry controlled by VL.
When the output is clamped, the negative input continues to
source a slewing current (ICLAMP) in an attempt to force the
output to the quiescent voltage defined by the input. QP5
must sink this current while clamping, because the -IN
current is always mirrored onto the high impedance node.
The clamping current is calculated as:
ICLAMP = (V-IN - VOUT CLAMPED)/300 + V-IN/RG.
As an example, a unity gain circuit with VIN = 2V, and VH =1V,
would have ICLAMP = (2V - 1V)/300 +2V/∞ = 3.33mA
(RG = ∞ because -IN is floated for unity gain applications).
Note that ICC will increase by ICLAMP when the output is
clamp limited.
1
2
3
4
8
7
6
5
+5V
10
F
0.1
F
VH
50
GND
R1
-5V
0.1
F
10
F
50
IN
OUT
VL
∞ (A
V = +1)
OR 0
(AV = +2)
FIGURE 2. MODIFIED EVALUATION BOARD SCHEMATIC
VH
+IN
VL
V+
GND
1
V-
OUT
TOP LAYOUT
BOTTOM LAYOUT
FIGURE 3. EVALUATION BOARD LAYOUT
+1
+IN
V-
V+
QP1
QN1
V-
QN3
QP3
QP4
QN2
QP2
QN4
QP5
QN5
Z
V+
-IN
VOUT
ICLAMP
RF = 300
(INTERNAL)
QP6
QN6
VH
R1
50K
(30K
FOR VL)
300
RG
(INTERNAL)
V-IN
200
FIGURE 4. HFA1113 SIMPLIFIED VH CLAMP CIRCUITRY
HFA1113
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