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參數(shù)資料
| 型號： | HFA1135IBZ96 |
| 廠商： | Intersil |
| 文件頁數(shù)： | 12/15頁 |
| 文件大小： | 0K |
| 描述： | IC OPAMP CFA 360MHZ LP 8-SOIC |
| 標(biāo)準(zhǔn)包裝： | 2,500 |
| 應(yīng)用： | 電流反饋 |
| 電路數(shù)： | 1 |
| -3db帶寬： | 360MHz |
| 轉(zhuǎn)換速率： | 1530 V/µs |
| 電流 - 電源： | 6.9mA |
| 電流 - 輸出 / 通道： | 60mA |
| 電壓 - 電源，單路/雙路(±)： | ±4.5 V ~ 5.5 V |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 8-SOIC（0.154"，3.90mm 寬） |
| 供應(yīng)商設(shè)備封裝： | 8-SOIC |
| 包裝： | 帶卷 (TR) |
6
Evaluation Board
The performance of the HFA1135 may be evaluated using
the HFA11XX evaluation board (part number
HFA11XXEVAL). Please contact your local sales office for
information. When evaluating this amplifier at a gain of +2,
the two 510
gain setting resistors on the evaluation board
should be changed to 250
.
The layout and schematic of the board are shown in Figure 2.
NOTE: The SOIC version may be evaluated in the DIP board by
using a SOIC-to-DIP adapter such as Aries Electronics part number
08-350000-10.
Limiting Operation
General
The HFA1135 features user programmable output clamps to
limit output voltage excursions. Limiting action is obtained by
applying voltages to the VH and VL terminals (pins 8 and 5)
of the amplifier. VH sets the upper output limit, while VL sets
the lower limit level. If the amplifier tries to drive the output
above VH, or below VL, the clamp circuitry limits the output
voltage at VH or VL (± the limit accuracy), respectively. The
low input bias currents of the limit pins allow them to be
driven by simple resistive divider circuits, or active elements
such as amplifiers or DACs.
Limit Circuitry
Figure 3 shows a simplified schematic of the HFA1135 input
stage, and the high limit (VH) circuitry. As with all current
feedback amplifiers, there is a unity gain buffer (QX1 - QX2)
between the positive and negative inputs. This buffer forces
-IN to track +IN, and sets up a slewing current of:
ISLEW = (V-IN - VOUT)/RF + V-IN/RG
This current is mirrored onto the high impedance node (Z) by
QX3-QX4, where it is converted to a voltage and fed to the
output via another unity gain buffer. If no limiting is utilized,
the high impedance node may swing within the limits defined
by QP4 and QN4. Note that when the output reaches its
quiescent value, the current flowing through -IN is reduced to
only that small current (-IBIAS) required to keep the output at
the final voltage.
Tracing the path from VH to Z illustrates the effect of the limit
voltage on the high impedance node. VH decreases by 2VBE
(QN6 and QP6) to set up the base voltage on QP5. QP5
begins to conduct whenever the high impedance node
reaches a voltage equal to QP5’s base voltage + 2VBE (QP5
and QN5). Thus, QP5 limits node Z whenever Z reaches VH.
R1 provides a pull-up network to ensure functionality with the
limit inputs floating. A similar description applies to the
symmetrical low limit circuitry controlled by VL.
BOARD SCHEMATIC
TOP LAYOUT
BOTTOM LAYOUT
FIGURE 2. EVALUATION BOARD SCHEMATIC AND LAYOUT
1
2
3
4
8
7
6
5
+5V
10
F
0.1
F
VH
50
GND
510
510
-5V
0.1
F
10
F
50
IN
OUT
VL
VH
+IN
VL
V+
GND
1
V-
OUT
+1
+IN
V-
V+
QP1
QN1
V-
QN3
QP3
QP4
QN2
QP2
QN4
QP5
QN5
Z
V+
-IN
VOUT
ILIMIT
RF
(EXTERNAL)
QP6
QN6
VH
R1
V-IN
200
FIGURE 3. HFA1135 SIMPLIFIED VH LIMIT CIRCUITRY
50k
HFA1135
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