參數(shù)資料
型號(hào)： HFA5253
廠商： Harris Corporation
英文描述： 800MHz, Ultra High-Speed Monolithic Pin Driver
中文描述： 800MHz的，超高速單片管腳驅(qū)動(dòng)
文件頁(yè)數(shù)： 2/18頁(yè)
文件大小： 527K
代理商： HFA5253
90
Pin Descriptions
NAME
FUNCTION
V
CC1
Positive Supply. Nominal value is 11.2V
±
0.2V. Reducing supply voltage below 11.0V will reduce positive output voltage swing.
The total supply voltage from V
CC1
to V
EE1
should not exceed 18.0V for normal operation or exceed 19.0V to prevent damage.
Harris recommends two wire bonds to this pad to provide the lowest possible impedance. In addition, power supply decoupling
chip capacitors of 470pF, 0.1
μ
F and a 10
μ
F tantalum are recommended. Do not connect the V
CC1
and V
CC2
pins together im-
mediately, rather run separate traces until they can be joined at a large bypass capacitor (0.1
μ
F || 10.0
μ
F).
V
EE1
Negative Supply. Nominal value is -6.4V
±
0.2V. A supply voltage more positive than -6.2V will reduce negative output voltage
swing. The total supply voltage from V
CC1
to V
EE1
should not exceed 18.0V for normal operation or exceed 19.0V to prevent
damage. Harris recommends two wire bonds to this pad to provide the lowest possible impedance. In addition, power supply de-
coupling chip capacitors of 470pF, 0.1
μ
F and a 10
μ
F tantalum are recommended. Do not connect the V
EE1
and V
EE2
pins to-
gether immediately, rather run separate traces until they can be joined at a large bypass capacitor (0.1
μ
F || 10.0
μ
F).
V
CC2
Output Stage Positive Supply. Nominal voltage and cautions are the same as for V
CC1
. Having decoupling chip capacitors close
to V
CC2
and V
EE2
is essential since large AC current will flow through this pad to the output during transients. Harris recommends
two wire bonds for this pad. Do not connect the V
CC1
and V
CC2
pins together immediately, rather run separate traces until they
can be joined at a large bypass capacitor (0.1
μ
F || 10.0
μ
F).
V
EE2
Output Stage Negative Supply. Nominal voltage and cautions are the same as for V
EE1
. Having decoupling chip capacitors close
to V
CC2
and V
EE2
is essential since large AC current will flow through this pad to the output during transients. Harris recommends
two wire bonds for this pad. Do not connect the V
EE1
and V
EE2
pins together immediately, rather run separate traces until they
can be joined at a large bypass capacitor (0.1
μ
F || 10.0
μ
F).
V
HIGH
Input Voltage High is used to set the output high level V
OH
. V
HIGH
is sensitive to capacitively coupled AC noise. Protection from
high frequency noise can be achieved with a low pass filter consisting of a 50
chip resistor and a 470pF chip capacitor. Without
this precaution the pin driver may oscillate due to feedback from the output through the PC board ground.
V
LOW
Input Voltage Low is used to set the output low level V
OL
. V
LOW
is sensitive to capacitively coupled AC noise. Protection from
high frequency noise can be achieved with a low pass filter consisting of a 50
chip resistor and a 470pF chip capacitor. Without
this precaution the pin driver may oscillate due to feedback from the output through the PC board ground.
V
OUT
Driver Output. The output impedance has been laser trimmed to match a 50
transmission line
±
2
. Custom output impedance
trimming is available (contact sales office for details) to provide the best match possible to your 50
system.
DATA, DATA
Differential Digital Inputs used to switch V
OUT
to the V
HIGH
or V
LOW
level. Harris recommends this input pair be driven by com-
plementary ECL signals to provide optimal switching speeds and timing accuracy. However a large Common Mode and Differen-
tial Voltage Range is provided to accommodate a variety of signals including single ended TTL and CMOS. When using single
ended signals the other input must be tied to an appropriate threshold voltage.
HIZ, HIZ
Differential Digital Inputs used to switch V
OUT
from an Active to a High Impedance State. Harris recommends that this input pair
be driven by complementary ECL signals to provide optimal switching speeds and timing accuracy. However a large Common
Mode and Differential Voltage Range is provided to accommodate a variety of signals including single ended TTL and CMOS.
When using single ended signals the other input must be tied to an appropriate threshold voltage.
+SRC
The Positive Slew Rate Control Pin adjusts the rising edge slew rate with an external current I
STEAL
. I
STEAL
draws current (0mA
to 10mA) from an internal current source limiting the rate of change of the high impedance node. Typically an external resistor to
GND is sufficient to set the slew rate at a desired level. Leaving the +SRC Pin open will give the highest speed performance. The
external current I
STEAL
for a resistor R
STEAL
connected from +SRC to GND may be calculated by: I
STEAL
= (V
CC
- 0.35)/R
STEAL
.
-SRC
The Negative Slew Rate Control Pin adjusts the falling edge slew rate with an external current I
STEAL
. I
STEAL
supplies current
(0mA to 10mA) to an internal current source limiting the amount of current being drawn from the circuit and thus limiting the rate
of change of the high impedance node. Typically an external resistor to GND is sufficient to set the slew rate at a desired level.
Leaving the -SRC Pin open will give the highest speed performance. The external current I
STEAL
for a resistor R
STEAL
connected
from -SRC to GND may be calculated by: I
STEAL
= (V
EE
+ 0.35)/R
STEAL
.
HFA5253
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