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| 型號： | HFBR-5112 |
| 英文描述： | Low Cost, Industry Standard FDDI MIC Transceivers(Narrow 1x13)(低價格，工業(yè)標(biāo)準(zhǔn) FDDI MIC收發(fā)器(狹長 1x13)) |
| 中文描述： | 成本低，行業(yè)標(biāo)準(zhǔn)FDDI的麥克風(fēng)收發(fā)器（窄1x13）（低價格，工業(yè)標(biāo)準(zhǔn)FDDI的麥克風(fēng)收發(fā)器（狹長1x13）） |
| 文件頁數(shù)： | 6/16頁 |
| 文件大小： | 278K |
| 代理商： | HFBR-5112 |
6
the worst-case jitter contribution
that the transceivers are allowed
to make to the overall system
jitter without violating the Annex
E allocation example. In practice,
the typical contribution of the
Agilent transceiver is well below
the maximum amount.
Recommended Handling
Precautions
It is advised that normal static
precautions be taken in the
handling and assembly of these
transceivers to prevent damage
which may be induced by
electrostatic discharge (ESD).
The HFBR-511X Series meets
MIL-STD-883C Method 3015.4
Class 2.
Care should be taken to avoid
shorting the receiver Data or
Signal Detect outputs directly to
ground without proper current-
limiting impedance.
Solder and Wash Process
Compatibility
Each transceiver is delivered with
a protective port plug inserted
into the MIC receptacle. This port
process plug protects the optical
subassembly during wave solder
and aqueous wash processing and
acts as a dust cover during
shipping. The port process plugs
have been tested up to and found
to withstand 110 psi and 190
°
F.
These transceivers are
compatible with either industry
standard wave- or hand-solder
processes.
Shipping Container
Each transceiver is packaged in a
shipping container designed to
protect it from mechanical and
ESD damage during shipment or
storage.
Board Layout–Decoupling
Circuit and Ground Planes
It is important to take care in the
layout of your circuit board to
achieve optimum performance
from these transceivers. Figure 7
provides a good example of
schematics for decoupling
circuits that work well with this
product. It is further recom-
mended that a contiguous ground
plane be provided in the circuit
board directly under the
transceiver to provide a low
inductance ground for signal
return current. This recommenda-
tion is in keeping with good high
frequency board layout practices.
Board Layout–Hole Pattern
The hole pattern shown in Figure
8 for the 2x11 package style
complies with the pin sizes
specified by the multisource
agreement. Hole patterns are also
provided for the Standard and
Narrow 1x13 package styles.
These drawings can be used as a
guide in the mechanical layout of
your circuit board.
Board Layout–Art Work
The Applications Engineering
group has developed Gerber file
artwork for various fiber optic
transceiver layouts. Contact your
local Agilent sales representative
for details.
Regulatory Compliance
These transceiver products are
intended to enable commercial
system designers to develop
equipment that complies with the
various international regulations
governing certification of Infor-
mation Technology Equipment.
See Table 1 for details. Additional
information is available from your
Agilent sales representative.
Figure 6. Bit Error Rate vs. Relative
Receiver Input Optical Power.
B
-6
4
1 x 10
-2
RELATIVE INPUT OPTICAL POWER – dB
-4
2
-2
0
1 x 10
-4
1 x 10
-6
1 x 10
-7
1 x 10
-8
2.5 x 10
-10
1 x 10
-11
1 x 10
-12
CONDITIONS:
1. 125 MBd
2. PRBS 2
7
-1
3. CENTER OF SYMBOL SAMPLING.
4. T
A
= 25° C
5. V
CC
= 5 Vdc
6. INPUT OPTICAL RISE/FALL TIMES = 1.0/2.1 ns.
1 x 10
-5
1 x 10
-3
CENTER OF
SYMBOL
Transceiver Jitter
Performance
The Agilent 1300 nm transceivers
are designed to operate per the
system jitter allocations stated in
Table E1 of Annex E of the FDDI
PMD standard.
The Agilent 1300 nm transmitters
will tolerate the worst-case input
electrical jitter allowed in the
table without violating the worst-
case output optical jitter
requirement of Sections 8.1
Active Output Interface of the
FDDI PMD standard.
The Agilent 1300 nm receivers
will tolerate the worst-case input
optical jitter allowed in Section
8.2 Active Input Interface of the
FDDI PMD standard without
violating the worst-case output
electrical jitter allowed in the
Table E1 of the Annex E.
The jitter specifications stated in
the following 1300 nm trans-
ceiver specification table are
derived from the values in Table
E1 of Annex E. They represent
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| HFBR-5113 | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:125 MBd ATM and Fast Ethernet Transceiver in Low Cost Standard 1x13 Package |
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| HFBR5204 | 制造商:Avago Technologies 功能描述: |
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