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參數(shù)資料
| 型號： | HFCT-5905E |
| 英文描述： | MT-RJ Duplex Single Mode Transceiver(MT-RJ 雙工單模式收發(fā)器) |
| 中文描述： | 噸，個RJ雙工單模收發(fā)器（噸，個RJ雙工單模式收發(fā)器） |
| 文件頁數(shù)： | 3/12頁 |
| 文件大小： | 161K |
| 代理商： | HFCT-5905E |
3
Functional Description
Receiver Section
Design
The receiver section contains an
InGaAs/InP photo detector and a
preamplifier mounted in an
optical subassembly. This optical
subassembly is coupled to a
postamp/decision circuit on a
separate circuit board.
The postamplifier is ac coupled
to the preamplifier as illustrated
in Figure 1. The coupling
capacitors are large enough to
pass the SONET/SDH test pattern
at 155 MBd without significant
distortion or performance
penalty. If a lower signal rate, or
a code which has significantly
more low frequency content is
used, sensitivity, jitter and pulse
distortion could be degraded.
Figure 1 also shows a filter
network which limits the
bandwidth of the preamp output
signal. The filter is designed to
bandlimit the preamp output
noise and thus improve the
receiver sensitivity.
These components will also
reduce the sensitivity of the
receiver as the signal bit rate is
increased above 155 MBd.
Noise Immunity
The receiver includes internal
circuit components to filter
power supply noise. Under some
conditions of EMI and power
supply noise, external power
supply filtering may be
necessary. If receiver sensitivity
is found to be degraded by power
supply noise, the filter network
illustrated in Figure 3 may be
used to improve performance.
The values of the filter
components are general
recommendations and may be
changed to suit a particular
system environment. Shielded
inductors are recommended.
Terminating the Outputs
The PECL Data outputs of the
receiver may be terminated with
the standard Thevenin-equivalent
50 ohm to V
CC
- 2 V termination.
Other standard PECL terminating
techniques may be used.
The two outputs of the receiver
should be terminated with
identical load circuits to avoid
unnecessarily large ac current in
V
CC
. If the outputs are loaded
identically the ac current is
largely nulled. The SD output of
the receiver is PECL logic and
must be loaded if it is to be used.
The signal detect circuit is much
slower that the data path, so the
ac noise generated by an
asymmetrical load is negligible.
Power consumption may be
reduced by using a higher than
normal load impedance for the
SD output. Transmission line
effects are not generally a
problem as the switching rate is
slow.
The Signal Detect Circuit
The signal detect circuit works
by sensing the peak level of the
received signal and comparing
this level to a reference.
Figure 1. Receiver Block Diagram
TRANS-
IMPEDANCE
PRE-
AMPLIFIER
FILTER
GND
AMPLIFIER
PECL
OUTPUT
BUFFER
PECL
OUTPUT
BUFFER
DATA OUT
SIGNAL
DETECT
CIRCUIT
SD
DATA OUT
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