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    參數(shù)資料
    型號(hào): HFDOM40B-384SX
    廠商: Hanbit Electronics Co.,Ltd.
    英文描述: 40Pin Flash Disk Module Min.8MB ~ Max.512MB, True IDE Interface Mode, 3.3V / 5.0V Operating
    中文描述: 40Pin盤模塊Min.8MB?Max.512MB,真正的IDE接口模式,3.3 / 5.0V工作
    文件頁(yè)數(shù): 6/10頁(yè)
    文件大?。?/td> 136K
    代理商: HFDOM40B-384SX
    HANBit HFDOM40B-xxxSx
    URL : www.hbe.co.kr 6 / 10 HANBit Electronics Co., Ltd
    .
    REV 1.0 (November.2002)
    Signal Descriptions
    Table 2.2 Signal Descriptions
    Signal Name
    Dir.
    Pin
    Description
    A[2:0]
    I
    33,35,36
    In True IDE Mode only A[2:0] are used to select the one of eight registers in
    the Task File, the remaining address lines should be grounded by the host.
    This input / output is the Pass Diagnostic signal in the Master / Slave
    handshake protocol.
    This signal used either to drive an
    LED
    whenever the Disk Module is being
    accessed or as indication of a second drive present. This signal is active low
    when the Disk Module is busy.
    CS0 is the chip select for the task file registers while CS2 is used to select
    the Alternate Status Register and the Device Control Register.
    All Task File operations occur in byte mode on the low order bus D00-D07
    while all data transfers are 16 bit using D00-D15.
    -PDIAG
    I/O
    34
    -DASP(
    LED
    )
    I/O
    39
    -CS0, -CS1
    I
    37,38
    D[15:00]
    I/O
    3,4,5,6,
    7,8,9,10,
    11,12,13,
    14,15,16,
    17,18
    GND
    --
    2,19,22,
    24,26,
    30,40,
    Ground.
    -IOR
    I
    25
    This is an I/O Read strobe generated by the host.
    The I/O Write strobe pulse is used to clock I/O data on the Card Data bus
    into the Storage Card controller registers when the Storage Card is
    configured to use the I/O interface. The clocking will occur on the negative to
    positive edge of the signal (trailing edge).
    -IOW
    I
    23
    IRQ
    O
    31
    In True IDE Mode signal is the active high Interrupt Request to the host.
    -RESET
    I
    1
    This input pin is the active low hardware reset from the host.
    IORDY
    O
    27
    This output signal may be used as IORDY.
    -IOIS16
    O
    32
    This output signal is asserted low when this device is expecting a word data
    transfer cycle.
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