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參數(shù)資料
| 型號(hào)： | HI-7151 |
| 廠商： | Intersil Corporation |
| 英文描述： | 128 MACROCELL 3.3 VOLT ISP CPLD |
| 中文描述： | 10位，高速，在A / D轉(zhuǎn)換器和保持跟蹤 |
| 文件頁(yè)數(shù)： | 6/17頁(yè) |
| 文件大?。?/td> | 854K |
| 代理商： | HI-7151 |
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6
AC Electrical Specifications
V+ = 5V
±
10%, V- = -5V
±
10%, V
REF
= 2.5V, T
A
= 25
o
C, f
CLK
= 300kHz, 50% Duty Cycle,
C
L
= 100pF (including stray for D0 - D9, OVR, HOLD, BUSY), Unless Otherwise Specified (Note 11)
PARAMETER
SYMBOL
NOTES
25
o
C
0
o
C to 75
o
C
-40
o
C to 85
o
C
UNITS
MIN
TYP
MAX
MIN
MAX
MIN
MAX
Clock Input Duty Cycle
D
5
45
50
55
45
55
45
55
%
Continuous Conversion Time
t
SPS
9
-
-
3tck
-
3tck
-
3tck
μ
s
9
60
-
10
60
10
60
10
μ
s
Slow Memory Mode Conversion
Time
t
CONV
5, 8
-
-
4tck
+0.9
-
4tck
+0.9
-
4tck
+0.9
μ
s
Continuous Throughput
t
CYC
9
-
-
f
CLK
/3
-
f
CLK
/3
-
f
CLK
/3/
3
sps
CLOCK Period
t
CK
-
-
1/f
CLK
-
-
-
-
-
CLOCK to HOLD Rise Delay
t
CKHR
5
150
290
500
140
525
120
525
ns
WR Pulse Width
t
WRL
5, 8, 10
200
113
tck/2
225
tck/2
225
tck/2
ns
WR to HOLD Delay
t
HOLD
5, 8
-
80
170
-
200
-
200
ns
Busy to Data
t
BD
5, 8
-
40
200
-
230
-
230
ns
WR to RD Active
t
WRD
5, 8
100
-
-
100
-
100
-
ns
CLOCK to HOLD Fall Delay
t
CKHF
5, 9
50
125
250
40
275
25
275
ns
HOLD to DATA change
t
DATA
5, 9
100
200
400
90
550
70
550
ns
RD LO to Active
t
RD
5, 13
-
75
150
-
190
-
190
ns
RD HI to Inactive
t
RX
5, 14
-
25
60
-
80
-
80
ns
HBE to DATA
t
AD
5
-
70
150
-
165
-
165
ns
CS to DATA
t
CD
5
-
95
180
-
210
-
210
ns
RD to BUSY
t
BUSY
5
-
35
200
-
200
-
200
ns
Rise Time
t
r
5, 12
-
50
100
-
125
-
125
ns
Fall Time
t
f
5, 12
-
45
100
-
120
-
120
ns
NOTES:
8. Slow memory mode timing.
9. Fast memory or DMA mode of operation, except the first conversion which is equal to t
CONV
.
10. Maximum specification to prevent multiple triggering with WR.
11. All input drive signals are specified with t
r
= t
f
≤
20ns and shall swing from V
IL
-0.4V to V
IH
+0.4V for all timing specifications. A signal is
considered to change state as it crosses a 1.4V threshold (except t
RD
and t
RX
).
12. t
r
and t
f
load is C
L
= 100pF (including stray capacitance) to DG and is measured from the 10 - 90% point.
13. t
RD
is the time required for the data output level to change by 10% in response to RD crossing a voltage level of 1.4V. High-Z to V
OH
is
measured with R
L
= 2.5k
and C
L
= 100pF (including stray) to DG. High-Z to V
OL
is measured with R
L
= 2.5k
to V+ and C
L
= 100pF
(including stray) to DG.
14. trx is the time required for the data output level to change by 10% in response to RD crossing a voltage level of 1.4V. V
OH
to High-Z is
measured with R
L
= 2.5k
and C
L
= 10pF (including stray) to DG. V
OL
to High-Z is measured with R
L
= 2.5 k
to V+ and C
L
= 10pF
(including stray) to DG.
HI-7151
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相關(guān)代理商/技術(shù)參數(shù) |
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| HI-7152 | 制造商:INTERSIL 制造商全稱:Intersil Corporation 功能描述:10-Bit High Speed A/D Converter with Track and Hold |
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