參數(shù)資料
型號(hào)： HI1396JCJ
廠商： HARRIS SEMICONDUCTOR
元件分類： ADC
英文描述： 8-Bit, 125 MSPS, Flash A/D Converter
中文描述： 1-CH 8-BIT FLASH METHOD ADC, PARALLEL ACCESS, CDIP42
文件頁(yè)數(shù)： 3/10頁(yè)
文件大小： 86K
代理商： HI1396JCJ
4-1158
Absolute Maximum Ratings
T
A
= 25
o
C
Supply Voltage (AV
EE
, DV
EE
) . . . . . . . . . . . . . . . . . . . . . . . . . . .-7V
Analog Input Voltage (V
IN
) . . . . . . . . . . . . . . . . . . . . . -2.7V to +0.5V
Reference Input Voltage
V
RT
, V
RB
, V
RM
. . . . . . . . . . . . . . . . . . . . . . . . . . . -2.7V to +0.5V
|V
RT
- V
RB
| . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .2.5V
Digital Input Voltage
CLK, CLK, MINV, LINV . . . . . . . . . . . . . . . . . . . . . . . -4V to +0.5V
|CLK-CLK| . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .2.7V
V
RM
Pin Input Current (I
VRM
) . . . . . . . . . . . . . . . . . . -3mA to +3mA
Digital Output Current (ID0 to ID7). . . . . . . . . . . . . . . -30mA to 0mA
Operating Conditions
(Note 1)
Thermal Information
Thermal Resistance (Typical, Note 1)
SBDIP Package. . . . . . . . . . . . . . . . . .
CLCC Package . . . . . . . . . . . . . . . . . .
Maximum Junction Temperature
Ceramic Packages. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 175
o
C
Maximum Storage Temperature Range (T
STG
) . . . .-65
o
C to 150
o
C
Maximum Lead Temperature (Soldering 10s). . . . . . . . . . . . 300
o
C
θ
JAo
C/W
45
45
θ
JCo
C/W
7
8
Temperature Ranges (Note 4)
SBDIP Package, T
A
. . . . . . . . . . . . . . . . . . . . . . . . -20
o
C to 75
o
C
CLCC Package, T
C
. . . . . . . . . . . . . . . . . . . . . . . . -20
o
C to 100
o
C
Supply Voltage Ranges
AV
EE
, DV
EE
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . -5.5V to -4.95V
AV
EE
- DV
EE
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.05V to 0.05V
AGND - DGND . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.05V to 0.05V
Reference Input Voltage
V
RT
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.1V to 0.1V
V
RB
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -2.2V to -1.8V
CAUTION: Stresses above those listed in “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress only rating and operation of
the device at these or any other conditions above those indicated in the operational sections of this specification is not implied.
Analog Input Voltage, V
IN
. . . . . . . . . . . . . . . . . . . . . . . .V
RB
to V
RT
Pulse Width of Clock
t
PW1
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4.0ns (Min)
t
PW0
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4.0ns (Min)
NOTE:
1.
θ
JA
is measured with the component mounted on an evaluation PC board in free air.
Electrical Specifications
T
A
= 25
o
C, AV
EE
= DV
EE
= -5.2V, V
RT
= 0V, V
RB
= -2V (Note 1)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
SYSTEM PERFORMANCE
Resolution
-
8
-
Bits
Integral Linearity Error, INL
HI1396JCJ, HI1396AIL
f
C
= 125 MSPS
-
±
0.3
±
0.5
LSB
Differential Linearity Error, DNL
HI1396JCJ, HI1396AIL
f
C
= 125 MSPS
-
-
±
0.5
LSB
ANALOG INPUT
Input Bandwidth
V
IN
= 2V
P-P
V
IN
= 1V + 0.07V
RMS
200
-
-
MHz
Analog Input Capacitance, C
IN
Analog Input Resistance, R
IN
Input Bias Current, I
IN
REFERENCE INPUTS
-
17
-
pF
50
190
-
k
μ
A
V
IN
= -1V
20
130
400
Reference Resistance, R
REF
Offset Voltage
E
OT
E
OB
DIGITAL INPUTS
75
110
155
V
RT
V
RB
8
19
32
mV
0
15
24
mV
Logic H Level, V
IH
Logic L Level, V
IL
Logic H Current, I
IH
Logic L Current, I
IL
Input Capacitance
-1.13
-
-
V
-
-
-1.50
V
Input Connected to -0.8V
0
-
50
μ
A
μ
A
Input Connected to -1.6V
0
-
50
-
7
-
pF
DIGITAL OUTPUTS
Logic H Level, V
OH
Logic L Level, V
OL
R
L
= 50
to -2V
R
L
= 50
to -2V
-1.10
-
-
V
-
-
-1.62
V
HI1396
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