參數(shù)資料
型號(hào)： HI2325
廠商： Intersil Corporation
英文描述： 3.3V Dual 8-Bit, 40MSPS A/D Converter with Internal Reference and Digital Clamp
中文描述： 3.3V雙8位，40MSPS A / D轉(zhuǎn)換內(nèi)部參考和數(shù)字鉗型轉(zhuǎn)換器
文件頁(yè)數(shù)： 5/7頁(yè)
文件大?。?/td> 58K
代理商： HI2325
5
Analog Input Bias Current, I
B
A or I
B
B
V
INA
/V
INB
= ART/BRT, ARB/BRB, DC
(Notes 2, 3)
-
-
-
μ
A
Full Power Input Bandwidth, FPBW
f
S
= 40MHz, (Note 2)
-
-
-
MHz
REFERENCE VOLTAGE INPUT
Reference Voltage Input Range
-
-
-
V
Total Reference Resistance, R
RIN
Reference Current, I
RIN
Self Bias
-
370
-
k
-
5.4
-
mA
V
RB
V
RT
-
0.54
-
-
1.9
-
SAMPLING CLOCK INPUT
Input Logic High Voltage, V
IH
Input Logic Low Voltage, V
IL
Input Logic High Current, I
IH
Input Logic Low Current, I
IL
Input Capacitance, C
IN
DIGITAL OUTPUTS
CLK
2.0
-
-
V
CLK
-
-
0.8
V
CLK, V
IH
= 3.3V
CLK, V
IL
= 0V
CLK
-
-
-
μ
A
-
-
-
μ
A
-
-
-
pF
Output Logic High Voltage, V
OH
Output Logic Low Voltage, V
OL
Output Logic High Voltage, V
OH
Output Logic Low Voltage, V
OL
Output Capacitance, C
OUT
TIMING CHARACTERISTICS
I
OH
= 100
μ
A; D
VDD
= 3.3V
I
OL
= 1.5mA; D
VDD
= 3.3V
I
OH
= 100
μ
A; D
VDD
= 3.0V
I
OL
= 100
μ
A; D
VDD
= 3.0V
-
-
-
V
-
-
-
V
-
-
-
V
-
-
-
V
-
-
-
pF
Aperture Delay, t
AP
Aperture Jitter, t
AJ
Data Output Hold, t
H
Data Output Delay, t
OD
Data Latency, t
LAT
Power-Up Initialization
-
4
-
ns
-
5
-
ps
RMS
ns
-
10.7
-
-
11.7
-
ns
For a Valid Sample (Note 2)
2
2
2
Cycles
Data Invalid Time (Note 2)
-
-
-
Cycles
Sample Clock Pulse Width (Low)
(Note 2)
11.25
12.5
-
ns
Sample Clock Pulse Width (High)
(Note 2)
11.25
12.5
-
ns
Sample Clock Duty Cycle Variation
-
±
5
-
%
POWER SUPPLY CHARACTERISTICS
Analog Supply Voltage, A
VDD
Digital Supply Voltage, D
VDD
Supply Current, I
DD
Power Dissipation
(Note 2)
3.0
3.3
3.6
V
(Note 2)
3.0
3.3
3.6
V
f
S
= 40MSPS
-
30.3
-
mA
-
100
-
mW
Offset Error Sensitivity,
V
OS
Gain Error Sensitivity,
FSE
A
VDD
or D
VDD
= 3.3V
±
5%
A
VDD
or D
VDD
= 3.3V
±
5%
-
±
0.125
-
LSB
-
±
0.15
-
LSB
NOTES:
2. Parameter guaranteed by design or characterization and not production tested.
3. With the clock low and DC input.
Electrical Specifications
A
VDD
= D
VDD
= +3.3V; V
IN
= 1.50V; f
S
= 40MSPS at 50% Duty Cycle;
C
L
= 10pF; T
A
= 25
o
C; Unless Otherwise Specified
(Continued)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNITS
HI2325
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