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參數(shù)資料
| 型號(hào)： | HI3-5700J-5 |
| 廠商： | INTERSIL CORP |
| 元件分類： | ADC |
| 英文描述： | 8-Bit, 20 MSPS Flash A/D Converter |
| 中文描述： | 1-CH 8-BIT FLASH METHOD ADC, PARALLEL ACCESS, PDIP28 |
| 封裝： | PLASTIC, DIP-28 |
| 文件頁數(shù)： | 10/12頁 |
| 文件大?。?/td> | 746K |
| 代理商： | HI3-5700J-5 |
4-1500
HI-5700
rate.
The signal source must absorb these transients prior to the
end of the sample period to ensure a valid signal for
conversion. Suitable broad band amplifiers or buffers which
exhibit low output impedance and high output drive include
the HA-5004, HA-5002, and HA-5003.
The signal source may drive above or below the power supply
rails, but should not exceed 0.5V beyond the rails or damage
may occur. Input voltages of -0.5V to +0.5 LSB are converted
to all zeroes; input voltages of V
REF
+ -0.5 LSB to V
DD
+0.5V
are converted to all ones with the Overflow bit set.
Full Scale Offset Error Adjustment
In applications where accuracy is of utmost importance,
three adjustments can be made; i.e., offset, gain, and
reference tap point trims. In general, offset and gain
correction can be done in the preamp circuitry.
Offset Adjustment
Offset correction can be done in the preamp driving the
converter by introducing a DC component to the input signal.
An alternate method is to adjust V
REF
- to produce the
desired offset. It is adjusted such that the 0 to 1 code
transition occurs at 0.5 LSB.
Gain Adjustment
In general, full scale error correction can be done in the
preamp circuitry by adjusting the gain of the op amp. An
alternate method is to adjust the V
REF
+ voltage. The
reference voltage is the ideal location.
Quarter Point Adjustment
The reference tap points are brought out for linearity
adjustment or creating a nonlinear transfer function if
desired. It is not necessary to decouple the
1
/
4
R,
1
/
2
R, and
3
/
4
R tap points in most applications.
Power Supplies
The HI-5700 operates nominally from 5V supplies but will
work from 3V to 6V. Power to the device is split such that
analog and digital circuits within the HI-5700 are powered
separately. The analog supply should be well regulated and
“clean” from significant noise, especially high frequency
noise. The digital supply should match the analog supply
within about 0.5V and should be referenced externally to the
analog supply at a single point. Analog and digital grounds
should not be separated by more that 0.5V. It is
recommended that power supply decoupling capacitors be
placed as close to the supply pins as possible. A
combination of 0.01
μ
F ceramic and 10
μ
F tantalum
capacitors is recommended for this purpose as shown in the
test circuit.
Reducing Power Consumption
Power dissipation in the HI-5700 is related to clock
frequency and clock duty cycle. For a fixed 50% clock duty
cycle, power may be reduced by lowering the clock
frequency. For a given conversion frequency, power may be
reduced by decreasing the Auto-Balance (
φ
1) portion of the
clock duty cycle. This relationship is illustrated in the
TABLE 3. CODE TABLE
CODE
DESCRIPTION
INPUT VOLTAGE
V
REF
+
= 4.0V
V
REF
- = 0.0V
(V)
DECIMAL
COUNT
BINARY OUTPUT CODE
MSB
LSB
OVF
D7
D6
D5
D4
D3
D2
D1
D0
Overflow (OVF)
4.000
511
1
1
1
1
1
1
1
1
1
Full Scale (FS)
3.9766
255
0
1
1
1
1
1
1
1
1
FS
-
1 LSB
3.961
254
0
1
1
1
1
1
1
1
0
3/4 FS
2.992
192
0
1
1
0
0
0
0
0
0
1/2 FS
1.992
128
0
1
0
0
0
0
0
0
0
1/4 FS
0.992
64
0
0
1
0
0
0
0
0
0
1 LSB
0.0078
1
0
0
0
0
0
0
0
0
1
Zero
0
0
0
0
0
0
0
0
0
0
0
The voltages listed above represent the ideal transition of each output code shown as a function of the reference voltage.
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