參數(shù)資料
型號: HI3026JCQ
廠商: Intersil
文件頁數(shù): 14/17頁
文件大小: 0K
描述: ADC FLASH 8BIT 120MSPS 48-PQFP
標(biāo)準(zhǔn)包裝: 60
位數(shù): 8
采樣率(每秒): 120M
數(shù)據(jù)接口: 并聯(lián)
轉(zhuǎn)換器數(shù)目: 1
電壓電源: 模擬和數(shù)字
工作溫度: -20°C ~ 75°C
安裝類型: 表面貼裝
封裝/外殼: 44-BQFP
供應(yīng)商設(shè)備封裝: 48-MQFP(12x12)
包裝: 托盤
輸入數(shù)目和類型: 1 個單端,單極
6
FIGURE 2. STRAIGHT MODE TIMING CHART (SELECT = GND)
FIGURE 3. ECL AND PECL SWITCHING LEVEL
Pin Descriptions
PIN NO
SYMBOL
I/O
TYPICAL
VOLTAGE LEVEL
EQUIVALENT CIRCUIT
DESCRIPTION
3, 10
AGND
GND
Analog Ground. Separated from the
digital ground.
5, 8
AVCC
+5V (Typ)
Analog Power Supply. Separated from
the digital power supply.
20, 29
32, 41
DGND1
DGND2
GND
Digital Ground.
19, 30
31, 42
DVCC1
DVCC2
+5V (Typ)
Digital Power Supply.
12
DGND3
+5V (Typ) (With a
Single Power Supply)
Digital Power Supply. Ground for ECL
input. -5V for PECL and TTL input.
GND (With Dual
Power Supplies)
Timing Diagrams
N - 1
N
N + 1
N + 2
N + 3
tDS
tPW1
tPW0
N - 4
2.0V
0.8V
2.0V
0.8V
N - 5
N - 3
N - 4
N - 2
N - 3
N - 1
N - 2
N
N - 1
tD02
8ns
2.0V
0.8V
tDCLK
RESET PULSE
CLK OUT
(CLK IS INVERTED AND OUTPUT)
P2D0 TO D7
P1D0 TO D7
CLK
VIN
t
VID
DGND3
VIH (MAX)
VIL
VTH (DGND3 - 1.2V)
VIH
VIL (MIN)
HI3026
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