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參數(shù)資料
| 型號(hào)： | HI3338 |
| 廠商： | Intersil Corporation |
| 英文描述： | 8-Bit, CMOS R2R D/A Converter |
| 中文描述： | 8位的CMOS R2R D / A轉(zhuǎn)換 |
| 文件頁數(shù)： | 5/8頁 |
| 文件大小： | 60K |
| 代理商： | HI3338 |
10-1468
Digital Signal Path
The digital inputs (LE, COMP, and D0 - D7) are of TTL
compatible HCT High Speed CMOS design: the loading is
essentially capacitive and the logic threshold is typically
1.5V.
The 8 data bits, D0 (weighted 2
0
) through D7 (weighted 2
7
),
are applied to Exclusive OR gates (see Functional Diagram).
The COMP (data complement) control provides the second
input to the gates: if COMP is high, the data bits will be
inverted as they pass through.
The input data and the LE (latch enable) signals are next
applied to a level shifter. The inputs, operating between the
levels of V
DD
and V
SS
, are shifted to operate between V
DD
and V
EE
. V
EE
optionally at ground or at a negative voltage,
will be discussed under bipolar operation. All further logic
elements except the output drivers operate from the V
DD
and V
EE
supplies.
The upper 3 bits of data, D5 through D7, are input to a 3-to-7
line bar graph encoder. The encoder outputs and D0 through
D4 are applied to a feedthrough latch, which is controlled by
LE (latch enable).
Latch Operation
Data is fed from input to output while LE is low: LE should be
tied low for non-clocked operation.
Non-clocked operation or changing data while LE is low is
not recommended for applications requiring low output
“glitch” energy: there is no guarantee of the simultaneous
changing of input data or the equal propagation delay of all
bits through the converter. Several parameters are given if
the converter is to be used in either of these modes: t
D2
gives the delay from the input changing to the output chang-
ing (10%), while t
SU2
and t
H
give the set up and hold times
(referred to LE rising edge) needed to latch data. See
Figures 1 and 2.
Clocked operation is needed for low “glitch” energy use.
Data must meet the given t
SU1
set up time to the LE falling
edge, and the t
H
hold time from the LE rising edge. The
delay to the output changing, t
D1
, is now referred to the LE
falling edge.
There is no need for a square wave LE clock; LE must only
meet the minimum t
W
pulse width for successful latch
operation. Generally, output timing (desired accuracy of
settling) sets the upper limit of usable clock frequency.
Output Structure
The latches feed data to a row of high current CMOS drivers,
which in turn feed a modified R2R ladder network.
The “N” channel (pull down) transistor of each driver plus
the bottom “2R” resistor are returned to V
REF
- this is the
(-) full-scale reference. The “P” channel (pull up) transistor
of each driver is returned to V
REF
+, the (+) full-scale
reference.
In unipolar operation, V
REF
- would typically be returned to
analog ground, but may be raised above ground (see specifi-
cations). There is substantial code dependent current that
flows from V
REF
+ to V
REF
- (see V
REF
+ input current in
specifications), so V
REF
- should have a low impedance path
to ground.
In bipolar operation, V
REF
- would be returned to a negative
voltage (the maximum voltage rating to V
DD
must be
observed). V
EE
, which supplies the gate potential for the
output drivers, must be returned to a point at least as nega-
tive as V
REF
-. Note that the maximum clocking speed
decreases when the bipolar mode is used.
Static Characteristics
The ideal 8-bit D/A would have an output equal to V
REF
-
with an input code of 00
HEX
(zero scale output), and an out-
put equal to 255/256 of V
REF
+ (referred to V
REF
-) with an
input code of FFHEX(full scale output). The difference
between the ideal and actual values of these two parameters
are the OFFSET and GAIN errors, respectively; see
Figure 3.
If the code into an 8-bit D/A is changed by 1 count, the
output should change by 1/255 (full-scale output-zero scale
output). A deviation from this step size is a differential linear-
ity error, see Figure 4. Note that the error is expressed in
fractions of the ideal step size (usually called an LSB). Also
note that if the (-) differential linearity error is less (in
Pin Descriptions
PIN
NAME
DESCRIPTION
1
D7
Most Significant Bit.
2
D6
Input
3
D5
Data
4
D4
Bits
5
D3
(High = True)
6
D2
7
D1
8
V
SS
Digital Ground.
9
D0
Least Significant Bit. Input Data Bit.
10
V
EE
Analog Ground.
11
V
REF
-
Reference Voltage Negative Input.
12
V
OUT
Analog Output.
13
V
REF
+
Reference Voltage Positive Input.
14
COMP
Data Complement Control input. Active High.
15
LE
Latch Enable Input. Active Low.
16
V
DD
Digital Power Supply, +5V.
HI3338
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