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參數(shù)資料
| 型號： | HI3338KIP |
| 廠商： | HARRIS SEMICONDUCTOR |
| 元件分類： | DAC |
| 英文描述： | TVS DUAL-UNI SGL-BI 300MW SOT-23 |
| 中文描述： | PARALLEL, 8 BITS INPUT LOADING, 0.02 us SETTLING TIME, 8-BIT DAC, PDIP16 |
| 文件頁數(shù)： | 7/8頁 |
| 文件大?。?/td> | 60K |
| 代理商： | HI3338KIP |
10-1470
FIGURE 5. HI3338 DYNAMIC TEST CIRCUIT
FIGURE 6. HI3338 AND CA3450 FOR DRIVING MULTIPLE COAXIAL LINES
CLOCK
8 DATA BITS
+5V
15
16
14
8
1-7, 9
LE
D0 - D7
V
DD
COMP
V
SS
HI3338
V
OUT
V
REF
+
V
EE
12
13
11
10
+5V
+2.5V
-2.5V
R1
R2
PROBE TIP
OR BNC
CONNECTOR
REMOTE
V
OUT
R3
V
REF
-
DIGITAL
GROUND
ANALOG
GROUND
+
+
+
FUNCTION
CONNECTOR
R1
R2
R3
V
OUT(P-P)
1V
Oscilloscope Display
Probe Tip
82
62
N/C
Match 93
Cable
BNC
75
160
93
1V
Match 75
Cable
BNC
18
130
75
1V
Match 50
Cable
BNC
Short
75
50
0.79V
NOTES:
1. V
OUT(P-P)
is approximate, and will vary as R
OUT
of D/A varies.
2. All drawn capacitors are 0.1
μ
F multilayer ceramic/4.7
μ
F tantalum.
3. Dashed connections are for unipolar operation. Solid connection are for bipolar operation.
NOTES:
1. Both V
REF
+pin and 392
resistor should be bypassed within
1
/
4
inch.
2. Keep nodal capacitance at CA3450 pin 3 as low as possible.
3. V
OUT
Range =
±
3V at CA3450.
CLOCK
8 DATA
BITS
+5V
15
16
14
8
1-7, 9
LE
D0 - D7
V
DD
COMP
V
SS
HI3338
V
OUT
V
REF
+
V
EE
12
13
11
10
R
V
REF
-
R
11
UP TO 5 OUTPUT LINES
FOR R = 75
, 3 LINES
FOR R = 50
V
OUT
1
V
OUT
N
+3.00V AT 25mA
4.7
μ
F
TAN
0.1
μ
F
CER.
4.7
μ
F TAN
+
4.7
μ
F
TAN
0.1
μ
F
CER.
0.1
μ
F
CER.
0.1
μ
F CER.
14
+6V
-6V
392
1%
392
1%
10k
1k
3
4, 5, 12, 13
R
R
+
+
+
V
OUT
=
±
1.5V
PEAK
6
7, 8
9
+
-
CA3450
ADJUST
OFFSET
5pF
4.7
μ
F
TAN
HI3338
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|---|---|
| HI33815 | 制造商:HARRIS 功能描述:* |
| HI3-381-5 | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:SPST Analog Switch |
| HI3-384-5 | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:DPST Analog Switch |
| HI3-387-5 | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:SPDT Analog Switch |
| HI3-390-5 | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:SPDT Analog Switch |
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