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參數(shù)資料
| 型號： | HI5630EVAL |
| 廠商： | Intersil Corporation |
| 英文描述： | Triple 8-Bit, 80MSPS A/D Converter with Internal Voltage Reference |
| 中文描述： | 三8位，80Msps的A / D轉(zhuǎn)換器內(nèi)部電壓基準(zhǔn) |
| 文件頁數(shù)： | 6/14頁 |
| 文件大?。?/td> | 125K |
| 代理商： | HI5630EVAL |
6
Over-Voltage Recovery
0.2V Overdrive
-
1
-
Cycle
Effective Number of Bits, ENOB
f
IN
= 1MHz (Figure 11)
f
IN
= 1MHz
f
IN
= 1MHz (Figure 12)
f
IN
= 1MHz
f
IN
= 1MHz (Figure 13)
-
7.6
-
Bits
Signal to Noise and Distortion Ratio, SINAD
-
47.8
-
dB
Signal to Noise Ratio, SNR
-
47.9
-
dB
Total Harmonic Distortion, THD
-
- 63
-
dB
Spurious Free Dynamic Range, SFDR
-
- 64
-
dB
Channel Crosstalk
-
75
-
dB
SAMPLING CLOCK INPUT
Note 3
Input Logic High Voltage, V
IH
Input Logic Low Voltage, V
IL
Input Logic High Current, I
IH
Input Logic Low Current, I
IL
Input Capacitance, C
IN
CLOCK OUTPUT
C
L
= 10pF (Note 3)
Output Logic High Voltage, V
OH
Output Logic Low Voltage, V
OL
Output Capacitance, C
COUT
DIGITAL OUTPUTS
C
L
= 10pF (Note 3)
Output Logic High Voltage, V
OH
Output Logic Low Voltage, V
OL
Output Capacitance, C
DOUT
TIMING CHARACTERISTICS
Figure 10
-
4
-
V
Figure 10
-
0.4
-
V
V
IH
= 4.5V
V
IL
= 0V
-10.0
-
+10.0
μ
A
μ
A
-10.0
-
+10.0
-
7
-
pF
I
OH
= 100
μ
A
I
OL
= 100
μ
A
4.0
-
-
V
-
-
0.8
V
-
7
-
pF
I
OH
= 100
μ
A; DV
DD
= 5V
I
OL
= 100
μ
A; DV
DD
= 5V
4.0
-
-
V
-
-
0.8
V
-
7
-
pF
Data Latency, t
LAT
Power-Up Initialization
For a Valid Sample
-
5
-
Cycles
Data Invalid Time
-
-
20
Cycles
Sample Clock Pulse Width (Low)
-
-
-
ns
Sample Clock Pulse Width (High)
-
-
-
ns
Sample Clock Duty Cycle Variation
Figure 9
-
±
5
-
%
POWER SUPPLY CHARACTERISTICS
Analog Supply Voltage, AV
DD
Digital Supply Voltage, DV
DD
Supply Current, I
TOTAL
Analog Current, IAV
DD
Digital5 Current, IDV
DD
Power Dissipation
4.75
5.0
5.25
V
4.75
5.0
5.25
V
-
348
-
mA
-
235
265
mA
-
113
-
mA
-
1.74
-
W
Standby Current
-
8
-
mA
Standby Power
-
40
-
mW
Offset Error PSRR,
V
OS
Gain Error PSRR,
FSE
AV
DD
or DV
DD
= 5V
±
5%
AV
DD
or DV
DD
= 5V
±
5%
-
±
0.4
±
0.15
-
LSB
-
-
LSB
NOTES:
2. Parameter guaranteed by design or characterization and not production tested.
3. With the clock low and DC input.
Electrical Specifications
AV
DD
= 5V, DV
DD
= 5V; Single Ended Inputs, V
RIN
= 2.5V; f
S
= 80MSPS at 50% Duty Cycle; C
L
= 10pF;
T
A
= 25
o
C; Unless Otherwise Specified
(Continued)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNITS
HI5630
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