3-46
Definition of Specifications
Integral Linearity Error, INL
, is the measure of the worst
case point that deviates from a best fit straight line of data
values along the transfer curve.
Differential Linearity Error, DNL,
is the measure of the
step size output deviation from code to code. Ideally the step
size should be 1 LSB. A DNL specification of 1 LSB or less
guarantees monotonicity.
Feedthru
is the measure of the undesirable switching noise
coupled to the output.
Output Voltage Full Scale Settling Time,
is the time
required from the 50% point on the clock input for a full scale
step to settle within an
1
/
2
LSB error band.
Output Voltage Small Scale Settling Time,
is the time
required from the 50% point on the clock input for a 100mV
step to settle within an
1
/
2
LSB error band. This is used by
applications reconstructing highly correlated signals such as
sine waves with more than 5 points per cycle.
Glitch Area, GE,
is the switching transient appearing on the
output during a code transition. It is measured as the area
under the curve and expressed as a Volt-Time specification.
Differential Gain,
A
V
, is the gain error from an ideal sine
wave with a normalized amplitude.
ENCODER
CONTROLLER
BASEBAND
BIT
STREAM
K9
C11
B11
C10
33 MSPS
CLK
CLK
MOD2
MOD1
HSP45106
SIN15
SIN14
SIN13
SIN12
SIN11
SIN10
SIN9
SIN8
SIN7
SIN6
SIN5
SIN4
SIN3
SIN2
SIN1
SIN0
R4
50
1
2
3
4
5
6
7
8
9
10
11
13
28
15
27
16
U2
D9 (MSB)
D8
D7
D6
D5
D4
D3
D2
D1
D0 (LSB)
DV
DD
V
CC
14
U1
CLK
INVERT
DV
SS
DV
SS
DV
EE
DV
EE
HI5721
-5.2V_D
AV
EE
AV
SS
I
OUT
I
OUT
/
REF IN
C AMP OUT
C AMP IN
RSET
ARET
REF OUT
20
21
23
24
26
25
17
19
18
22
R1
64
R1
64
+
R1
1960
C2
1.0
μ
F
C1
0.01
μ
F
-5.2V_A
-5.2V_A
FILTER
TO RF
UP-CONVERT
STAGE
L2
10
μ
H
L1
10
μ
H
-5.2V_A
-5.2V_D
MOD0
A11
F10
F9
F11
H11
G11
G9
J11
G10
D10
J10
K11
B8
A8
B6
B7
A7
C7
C6
A6
A5
C5
A4
B4
A3
A2
B3
A1
B10
B9
A10
E11
E9
H10
K2
J2
V
CC
V
CC
V
CC
PMSEL
ENPOREG#
ENOFREG#
ENCFREG#
ENPHAC#
ENTIREG#
INHOFR#
INITPAC#
INITTAC#
TEST
PARSER#
BINFMT#
C15_MSB
C4
C13
C12
C11
C10
C9
C8
C7
C6
C5
C4
C3
C2
C1
C0
A2
A1
A0
CS#
WR#
PACI#
OES#
OEC#
DACSTRB#
L1
K3
L2
L3
L4
J5
K5
L5
K6
J6
J7
L7
L6
L8
K8
L9
L10
COS15
COS14
COS13
COS12
COS11
COS10
COS9
COS8
COS7
COS6
COS5
COS4
COS3
COS2
COS1
COS0
TICO#
C2
B1
C1
D1
E3
E2
E1
F2
F3
G3
G1
G2
H1
H2
J1
K1
B2
FIGURE 25. PSK MODULATOR USING THE HI5721 AND THE HSP45106 12-BIT NCO
-5.2V_A
HI5721