參數(shù)資料
型號(hào): HI5728EVAL1
廠商: Intersil Corporation
英文描述: 10-Bit, 125/60MSPS, Dual High Speed CMOS D/A Converter
中文描述: 10位,125/60MSPS,雙路高速CMOS D / A轉(zhuǎn)換
文件頁數(shù): 15/17頁
文件大?。?/td> 207K
代理商: HI5728EVAL1
15
Definition of Specifications
Integral Linearity Error, INL
, is the measure of the worst
case point that deviates from a best fit straight line of data
values along the transfer curve.
Differential Linearity Error, DNL,
is the measure of the
step size output deviation from code to code. Ideally the step
size should be 1 LSB. A DNL specification of 1 LSB or less
guarantees monotonicity.
Output Settling Time,
is the time required for the output
voltage to settle to within a specified error band measured
from the beginning of the output transition. The
measurement was done by switching from code 0 to 256, or
quarter scale. Termination impedance was 25
due to the
parallel resistance of the output 50
and the oscilloscope’s
50
input. This also aids the ability to resolve the specified
error band without overdriving the oscilloscope.
Singlet Glitch Area,
is the switching transient appearing on
the output during a code transition. It is measured as the
area under the overshoot portion of the curve and is
expressed as a Volt-Time specification. This is tested under
the same conditions as ‘Output Settling Time.’
Timing Diagrams
FIGURE 39. OUTPUT SETTLING TIME DIAGRAM
FIGURE 40. PEAK GLITCH AREA (SINGLET) MEASUREMENT
METHOD
FIGURE 41. PROPAGATION DELAY, SETUP TIME, HOLD TIME AND MINIMUM PULSE WIDTH DIAGRAM
CLK
D9-D0
I
OUT
50%
t
SETT
1 LSB ERROR BAND
t
PD
V
t(ps)
HEIGHT (H)
WIDTH (W)
GLITCH AREA =
1
/
2
(H x W)
CLK
D9-D0
I
OUT
50%
t
PW1
t
PW2
t
SU
t
HLD
t
SU
t
SU
t
PD
t
PD
t
PD
t
HLD
t
HLD
t
SETT
t
SETT
t
SETT
HI5728
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PDF描述
HI5728 10-Bit, 125/60MSPS, Dual High Speed CMOS D/A Converter
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相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
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