參數(shù)資料
型號(hào): HI5728IN
廠商: HARRIS SEMICONDUCTOR
元件分類: DAC
英文描述: 10-Bit, 125/60MSPS, Dual High Speed CMOS D/A Converter
中文描述: DUAL, PARALLEL, WORD INPUT LOADING, 0.035 us SETTLING TIME, 10-BIT DAC, PQFP48
文件頁數(shù): 4/17頁
文件大?。?/td> 207K
代理商: HI5728IN
4
Pin Descriptions
PIN NO.
PIN NAME
PIN DESCRIPTION
39-30
QD9 (MSB) Through
QD0 (LSB)
Digital Data Bit 9, the Most Significant Bit through Digital Data Bit 0, the Least Significant Bit, of the Q
channel.
1-6, 48-46
ID9 (MSB) Through
ID0 (LSB)
Digital Data Bit 9, the Most Significant Bit through Digital Data Bit 0, the Least Significant Bit, of the I chan-
nel.
8
SLEEP
ControlPinforPower-Downmode.SleepModeisactivehigh;ConnecttogroundforNormalMode.Sleep
pin has internal 20
μ
A active pull-down current.
15
REFLO
Connect to analog ground to enable internal 1.2V reference or connect to AV
DD
to disable.
23
REFIO
Reference voltage input if internal reference is disabled and reference voltage output if internal reference is
enabled. Use 0.1
μ
F cap to ground when internal reference is enabled.
22
FSADJ
Full Scale Current Adjust. Use a resistor to ground to adjust full scale output current. Full Scale Output
Current Per Channel = 32 x I
FSADJ
.
14, 24
ICOMP1, QCOMP1
Reduces noise. Connect each to AV
DD
with 0.1
μ
F capacitor near each pin. The ICOMP1 and QCOMP1
pins MUST be tied together externally.
13, 18, 19, 25
AGND
Analog Ground Connections.
17
IOUTB
The complimentary current output of the I channel. Bits set to all 0s gives full scale current.
16
IOUTA
Current output of the I channel. Bits set to all 1s gives full scale current.
20
QOUTB
The complimentary current output of the Q channel. Bits set to all 0s gives full scale current.
21
QOUTA
Current output of the Q channel. Bits set to all 1s gives full scale current.
11, 27
NC
No Connect. Recommended: connect to ground.
12, 26
AV
DD
Analog Supply (+2.7V to +5.5V).
10, 28, 41, 44
DGND
Digital Ground.
9, 29, 40, 45
DV
DD
Supply voltage for digital circuitry (+2.7V to +5.5V).
43
ICLK
Clock input for I channel. Positive edge of clock latches data.
42
QCLK
Clock input for Q channel. Positive edge of clock latches data.
HI5728
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