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參數(shù)資料
| 型號(hào)： | HI5731-EVS |
| 廠商： | Intersil Corporation |
| 英文描述： | 12-Bit, 100 MSPS, High Speed D/A Converter |
| 中文描述： | 12位，100 MSPS的，高速D / A轉(zhuǎn)換 |
| 文件頁(yè)數(shù)： | 10/15頁(yè) |
| 文件大?。?/td> | 370K |
| 代理商： | HI5731-EVS |
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3-10
Multiplying Capability
The HI5731 can operate in two different multiplying
configurations. For frequencies from DC to 100kHz, a signal
of up to 0.6V
P-P
can be applied directly to the REF OUT pin
as shown in Figure 23.
The signal must have a DC value such that the peak
negative voltage equals -1.25V. Alternately, a capacitor can
be placed in series with REF OUT if DC multiplying is not
required. The lower input bandwidth can be calculated using
the following formula:
For multiplying frequencies above 100kHz, the CTRL IN pin
can be driven directly as seen in Figure 24.
The nominal input/output relationship is defined as:
V
In order to prevent the full scale output current from
exceeding 20.48mA, the R
SET
resistor must be adjusted
according to the following equation:
16V
-----------------------------------------------------------------------------------------------
.
=
The circuit in Figure 24 can be tuned to adjust the lower
cutoff frequency by adjusting capacitor values. Table 1 below
illustrates the relationship.
Also, the input signal must be limited to 1V
P-P
to avoid
distortion in the DAC output current caused by excessive
modulation of the internal current sources.
Outputs
The outputs I
OUT
and I
OUT
are complementary current
outputs. Current is steered to either I
OUT
or I
OUT
in
proportion to the digital input code. The sum of the two
currents is always equal to the full scale current minus one
LSB. The current output can be converted to a voltage by
using a load resistor. Both current outputs should have the
same load resistor (64
typically). By using a 64
load on
the output, a 50
effective output resistance (R
OUT
) is
achieved due to the 227
(
±
15%) parallel resistance seen
looking back into the output. This is the nominal value of the
R2R ladder of the DAC. The 50
output is needed for
matching the output with a 50
line. The load resistor should
be chosen so that the effective output resistance (R
OUT
)
matches the line resistance. The output voltage is:
V
OUT
= I
OUT
x R
OUT
.
I
OUT
is defined in the reference section. I
OUT
is not trimmed
to 12 bits, so it is not recommended that it be used in
conjunction with I
OUT
in a differential-to-single-ended
application. The compliance range of the output is from -
1.25V to 0V, with a 1V
P-P
voltage swing allowed within this
range.
Settling Time
The settling time of the HI5731 is measured as the time it
takes for the output of the DAC to settle to within a
1
/
2
LSB
error band of its final value during a full scale (code 0000...
to 1111.... or 1111... to 0000...) transition. All claims made by
Intersil with respect to the settling time performance of the
HI5731 have been fully verified by the National Institute of
Standards and Technology (NIST) and are fully traceable.
Glitch
The output glitch of the HI5731 is measured by summing the
area under the switching transients after an update of the
DAC. Glitch is caused by the time skew between bits of the
incoming digital data. Typically, the switching time of digital
inputs are asymmetrical meaning that the turn off time is
FIGURE 23. LOW FREQUENCY MULTIPLYING BANDWIDTH
CIRCUIT
REF OUT
HI5731
C
IN
(OPTIONAL)
0.01
μ
F
RSET
V
IN
CTRL OUT
CTRL IN
AV
EE
C
IN
IN
)
-------------------------------------------
.
=
FIGURE 24. HIGH FREQUENCY MULTIPLYING BANDWIDTH
CIRCUIT
HI5731
CTRL IN
V
IN
CTRL OUT
AV
EE
200
C
2
C
1
50
I
OUT
-------------
.
=
R
SET
I
OUT
(FULL SCALE)
)
-----------------------------
–
TABLE 1. CAPACITOR SELECTION
f
IN
C1
C2
100kHz
0.01
μ
F
1
μ
F
>1MHz
0.001
μ
F
0.1
μ
F
TABLE 2.
INPUT CODING vs CURRENT OUTPUT
INPUT CODE (D11-D0)
I
OUT
(mA)
I
OUT
(mA)
1111 1111 1111
-20.48
0
1000 0000 0000
-10.24
-10.24
0000 0000 0000
0
-20.48
HI5731
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