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參數(shù)資料
| 型號： | HI5731BIBZ |
| 廠商： | Intersil |
| 文件頁數(shù)： | 3/17頁 |
| 文件大小： | 0K |
| 描述： | DAC 12BIT 100MHZ 5.2V 28-SOIC |
| 標準包裝： | 26 |
| 設(shè)置時間： | 20ns |
| 位數(shù)： | 12 |
| 數(shù)據(jù)接口： | 并聯(lián) |
| 轉(zhuǎn)換器數(shù)目： | 1 |
| 電壓電源： | 模擬和數(shù)字，雙 ± |
| 功率耗散（最大）： | 650mW |
| 工作溫度： | -40°C ~ 85°C |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 28-SOIC（0.295"，7.50mm 寬） |
| 供應(yīng)商設(shè)備封裝： | 28-SOIC W |
| 包裝： | 管件 |
| 輸出數(shù)目和類型： | 2 電流，單極 |
| 采樣率（每秒）： | 100M |
11
be chosen so that the effective output resistance (ROUT)
matches the line resistance. The output voltage is:
VOUT = IOUT x ROUT.
IOUT is defined in the reference section. IOUT is not trimmed
to 12 bits, so it is not recommended that it be used in
conjunction with IOUT in a differential-to-single-ended
application. The compliance range of the output is from -
1.25V to 0V, with a 1VP-P voltage swing allowed within this
range.
Settling Time
The settling time of the HI5731 is measured as the time it
takes for the output of the DAC to settle to within a ± 1/2 LSB
error band of its final value during a full scale (code 0000...
to 1111.... or 1111... to 0000...) transition. All claims made by
Intersil with respect to the settling time performance of the
HI5731 have been fully verified by the National Institute of
Standards and Technology (NIST) and are fully traceable.
Glitch
The output glitch of the HI5731 is measured by summing the
area under the switching transients after an update of the
DAC. Glitch is caused by the time skew between bits of the
incoming digital data. Typically, the switching time of digital
inputs are asymmetrical meaning that the turn off time is
faster than the turn on time (TTL designs). Unequal delay
paths through the device can also cause one current source
to change before another. In order to minimize this, the
Intersil HI5731 employes an internal register, just prior to the
current sources, which is updated on the clock edge. Lastly,
the worst case glitch on traditional D/A converters usually
occurs at the major transition (i.e., code 2047 to 2048).
However, due to the split architecture of the HI5731, the
glitch is moved to the 255 to 256 transition (and every
subsequent 256 code transitions thereafter). This split R/2R
segmented current source architecture, which decreases the
amount of current switching at any one time, makes the
glitch practically constant over the entire output range. By
making the glitch a constant size over the entire output range
this effectively integrates this error out of the end application.
In measuring the output glitch of the HI5731 the output is
terminated into a 64
load. The glitch is measured at any
one of the current cell carry (code 255 to 256 transition or
any multiple thereof) throughout the DACs output range.
The glitch energy is calculated by measuring the area under
the voltage-time curve. Figure 26 shows the area considered
as glitch when changing the DAC output. Units are typically
specified in picoVolt-seconds (pV-s).
Applications
Bipolar Applications
To convert the output of the HI5731 to a bipolar 4V swing,
the following applications circuit is recommended. The
reference can only provide 125
A of drive, so it must be
buffered to create the bipolar offset current needed to
generate the -2V output with all bits ‘off’. The output current
must be converted to a voltage and then gained up and
offset to produce the proper swing. Care must be taken to
compensate for the voltage swing and error.
TABLE 2.
INPUT CODING vs CURRENT OUTPUT
INPUT CODE (D11-D0)
IOUT (mA)
1111 1111 1111
-20.48
0
1000 0000 0000
-10.24
0000 0000 0000
0
-20.48
(21) IOUT
100MHz
LOW PASS
FILTER
SCOPE
HI5731
64
50
FIGURE 25. GLITCH TEST CIRCUIT
FIGURE 26. MEASURING GLITCH ENERGY
a (mV)
t (ns)
GLITCH ENERGY = (
a x t)/2
HI5731
REF OUT
IOUT
1/
2 CA2904
+
-
+
-
+
-
50
5k
1/
2 CA2904
5k
60
240
240
HFA1100
VOUT
0.1
F
FIGURE 27. BIPOLAR OUTPUT CONFIGURATION
(21)
(26)
HI5731
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