參數(shù)資料
型號： HI5731BIP
廠商： HARRIS SEMICONDUCTOR
元件分類： DAC
英文描述： LOW SIGNAL RELAY
中文描述： PARALLEL, WORD INPUT LOADING, 0.02 us SETTLING TIME, 12-BIT DAC, PDIP28
文件頁數(shù)： 4/15頁
文件大?。?/td> 370K
代理商： HI5731BIP
3-4
Internal Reference Load Regulation
Input Impedance at REF OUT pin
Amplifier Large Signal Bandwidth (0.6V
P-P
)
Amplifier Small Signal Bandwidth (0.1V
P-P
)
Reference Input Impedance
Reference Input Multiplying Bandwidth (CTL IN)
I
REF
= 0 to I
REF
= -125
μ
A
(Note 3)
Sine Wave Input, to Slew Rate Limited (Note 3)
Sine Wave Input, to -3dB Loss (Note 3)
(Note 3)
R
L
= 50
, 100mV Sine Wave, to -3dB Loss at I
OUT
(Note 3)
-
-
-
-
-
-
50
1.4
3
10
12
200
-
-
-
-
-
-
μ
V
k
MHz
MHz
k
MHz
DIGITAL INPUTS (D9-D0, CLK, INVERT)
Input Logic High Voltage, V
IH
Input Logic Low Voltage, V
IL
Input Logic Current, I
IH
Input Logic Current, I
IL
Digital Input Capacitance, C
IN
TIMING CHARACTERISTICS
Data Setup Time, t
SU
Data Hold Time, t
HLD
Propagation Delay Time, t
PD
CLK Pulse Width, t
PW1
, t
PW2
POWER SUPPLY CHARACTERISTICS
I
EEA
I
EED
I
CCD
Power Dissipation
Power Supply Rejection Ratio
NOTES:
2. Gain Error measured as the error in the ratio between the full scale output current and the current through R
SET
(typically 1.28mA). Ideally the
ratio should be 16.
3. Parameter guaranteed by design or characterization and not production tested.
4. All devices are 100% tested at 25
o
C. 100% production tested at temperature extremes for military temperature devices, sample tested for
industrial temperature devices.
5. Dynamic Range must be limited to a 1V swing within the compliance range.
Timing Diagrams
(Note 4)
(Note 4)
(Note 4)
(Note 4)
(Note 3)
2.0
-
-
-
-
-
-
-
-
-
V
V
μ
A
μ
A
pF
0.8
400
700
-
3.0
See Figure 1 (Note 3)
See Figure 1 (Note 3)
See Figure 1 (Note 3)
See Figure 1 (Note 3)
3.0
0.5
-
3.0
2.0
0.25
4.5
-
-
-
-
-
ns
ns
ns
ns
(Note 4)
(Note 4)
(Note 4)
(Note 4)
V
CC
±
5%, V
EE
±
5%
-
-
-
-
-
42
70
13
650
5
50
85
20
-
-
mA
mA
mA
mW
μ
A/V
FIGURE 1. FULL SCALE SETTLING TIME DIAGRAM
FIGURE 2. PEAK GLITCH AREA (SINGLET) MEASUREMENT
METHOD
Electrical Specifications
AV
EE
, DV
EE
= -4.94 to -5.46V, V
CC
= +4.75 to +5.25V, V
REF
= Internal
T
A
= 25
o
C for All Typical Values
(Continued)
PARAMETER
TEST CONDITIONS
HI5731BI
T
A
= -40
o
C TO 85
o
C
MIN
TYP
UNITS
MAX
CLK
D11-D0
I
OUT
50%
t
SETT
±
1
/
2
LSB ERROR BAND
t
PD
V
t(ps)
HEIGHT (H)
WIDTH (W)
GLITCH AREA =
1
/
2
(H x W)
HI5731
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