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參數(shù)資料
| 型號： | HI5760IAZ |
| 廠商： | Intersil |
| 文件頁數(shù)： | 12/18頁 |
| 文件大小： | 0K |
| 描述： | CONV D/A 10-BIT 125MSPS 28-TSSOP |
| 標(biāo)準(zhǔn)包裝： | 500 |
| 設(shè)置時(shí)間： | 35ns |
| 位數(shù)： | 10 |
| 數(shù)據(jù)接口： | 并聯(lián) |
| 轉(zhuǎn)換器數(shù)目： | 1 |
| 電壓電源： | 模擬和數(shù)字 |
| 功率耗散（最大）： | 165mW |
| 工作溫度： | -40°C ~ 85°C |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 28-TSSOP（0.173"，4.40mm 寬） |
| 供應(yīng)商設(shè)備封裝： | 28-TSSOP |
| 包裝： | 管件 |
| 輸出數(shù)目和類型： | 2 電流，單極 |
| 采樣率（每秒）： | 125M |
3
Absolute Maximum Ratings
Thermal Information
Digital Supply Voltage DVDD to DCOM . . . . . . . . . . . . . . . . . +5.5V
Analog Supply Voltage AVDD to ACOM . . . . . . . . . . . . . . . . . +5.5V
Grounds, ACOM TO DCOM . . . . . . . . . . . . . . . . . . -0.3V To + 0.3V
Digital Input Voltages (D9-D0, CLK, SLEEP) . . . . . . DVDD + 0.3V
Internal Reference Output Current
. . . . . . . . . . . . . . . . . . . . . . . ±50A
Reference Input Voltage Range. . . . . . . . . . . . . . . . . . AVDD + 0.3V
Analog Output Current (IOUT) . . . . . . . . . . . . . . . . . . . . . . . . . 24mA
Operating Conditions
Temperature Range. . . . . . . . . . . . . . . . . . . . . . . . . . -40oC to 85oC
Thermal Resistance (Typical, Note 1)
θJA(oC/W)
SOIC Package . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
75
TSSOP Package . . . . . . . . . . . . . . . . . . . . . . . . . . .
135
Maximum Junction Temperature
HI5760 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 150oC
Maximum Storage Temperature Range . . . . . . . . . -65oC to 150oC
Maximum Lead Temperature (Soldering 10s) . . . . . . . . . . . . . 300oC
(SOIC - Lead Tips Only)
CAUTION: Stresses above those listed in “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress only rating and operation of the
device at these or any other conditions above those indicated in the operational sections of this specification is not implied.
NOTE:
1.
JA is measured with the component mounted on an evaluation PC board in free air.
Electrical Specifications
AVDD = DVDD = +5V, VREF = Internal 1.2V, IOUTFS = 20mA, TA = 25
oC for All Typical Values
PARAMETER
TEST CONDITIONS
HI5760
TA = -40
oC TO 85oC
UNITS
MIN
TYP
MAX
SYSTEM PERFORMANCE
Resolution
10
-
Bits
Integral Linearity Error, INL
“Best Fit” Straight Line (Note 7)
-1
±0.5
+1
LSB
Differential Linearity Error, DNL
(Note 7)
-0.5
±0.25
+0.5
LSB
Offset Error, IOS
(Note 7)
-0.025
+0.025
% FSR
Offset Drift Coefficient
(Note 7)
-
0.1
-
ppm
FSR/oC
Full Scale Gain Error, FSE
With External Reference (Notes 2, 7)
-10
% FSR
With Internal Reference (Notes 2, 7)
-10
±1+10
% FSR
Full Scale Gain Drift
With External Reference (Note 7)
-
±50
-
ppm
FSR/oC
With Internal Reference (Note 7)
-
±100
-
ppm
FSR/oC
Full Scale Output Current, IFS
2-
20
mA
Output Voltage Compliance Range
(Note 3)
-0.3
-
1.25
V
DYNAMIC CHARACTERISTICS
Maximum Clock Rate, fCLK
(Note 3)
125
-
MHz
Output Settling Time, (tSETT)
0.2% (
±1 LSB, equivalent to 9 Bits) (Note 7)
-
20
-
ns
0.1% (
±1/2 LSB, equivalent to 10 Bits) (Note 7)
-
35
-
ns
Singlet Glitch Area (Peak Glitch)
RL = 25 (Note 7)
-
5
-
pVs
Output Rise Time
Full Scale Step
-
1.0
-
ns
Output Fall Time
Full Scale Step
-
1.5
-
ns
Output Capacitance
-10
-
pF
Output Noise
IOUTFS = 20mA
-
50
-
pA/
√Hz
IOUTFS = 2mA
-
30
-
pA/
√Hz
HI5760
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