參數(shù)資料
型號： HI5762/6IN
廠商： Intersil
文件頁數(shù)： 3/16頁
文件大?。?/td> 0K
描述： CONV A/DDUAL 10BIT 60MSPS 44MQFP
標準包裝： 96
位數(shù)： 10
采樣率（每秒）： 60M
數(shù)據(jù)接口： 并聯(lián)
轉(zhuǎn)換器數(shù)目： 8
功率耗散（最大）： 670mW
電壓電源： 模擬和數(shù)字
工作溫度： -40°C ~ 85°C
安裝類型： 表面貼裝
封裝/外殼： 44-QFP
供應商設(shè)備封裝： 44-MQFP（10x10）
包裝： 管件
輸入數(shù)目和類型： 4 個單端，單極；8 個差分，雙極
11
FN4318.3
January 22, 2010
Detailed Description
Theory of Operation
The HI5762 is a dual 10-bit fully differential sampling pipeline
A/D converter with digital error correction logic. Figure 15
depicts the circuit for the front-end differential-in-differential-
out sample-and-hold (S/H) amplifiers. The switches are
controlled by an internal sampling clock which is a
non-overlapping two phase signal
, Φ1 and Φ2, derived from
the master sampling clock. During the sampling phase,
Φ1,
the input signal is applied to the sampling capacitors, CS. At
the same time the holding capacitors, CH, are discharged to
analog ground. At the falling edge of
Φ1 the input signal is
sampled on the bottom plates of the sampling capacitors. In
the next clock phase,
Φ2, the two bottom plates of the
sampling capacitors are connected together and the holding
capacitors are switched to the op amp output nodes. The
charge then redistributes between CS and CH completing one
sample-and-hold cycle. The front end sample-and-hold output
is a fully-differential, sampled-data representation of the
analog input. The circuit not only performs the sample-and-
hold function but will also convert a single-ended input to a
fully-differential output for the converter core. During the
sampling phase, the I/QIN pins see only the on-resistance of a
switch and CS. The relatively small values of these
components result in a typical full power input bandwidth of
250MHz for the converter.
FIGURE 13. SUPPLY CURRENT vs TEMPERATURE
FIGURE 14. 2048 POINT FFT PLOT
Typical Performance Curves (Continued)
SUP
P
LY
CU
RRE
N
T
(mA)
0
140
120
100
80
60
40
20
TEMPERATURE (°C)
020
40
60
80
-20
-40
fS = 60MSPS
1MHz < fIN < 15MHz
AICC
ICC
DICC1
DICC2
DICC3
0
-10
-20
-30
-40
-50
-60
-70
-80
-90
-100
0
100
200 300
400 500
600
700
800
900
1023
FREQUENCY (BIN)
dB
fS = 60MSPS
fIN = 10MHz
TA = +25°C
TABLE 1. A/D CODE TABLE
CODE CENTER
DESCRIPTION
DIFFERENTIAL INPUT
VOLTAGE
(I/QIN+ - I/QIN-)
OFFSET BINARY OUTPUT CODE
MSB
LSB
I/QD9 I/QD8 I/QD7 I/QD6 I/QD5 I/QD4 I/QD3 I/QD2 I/QD1 I/QD0
+Full Scale (+FS) -1/4LSB
0.499756V
1
+FS
- 11/4LSB
0.498779V
1
0
+3/4LSB
732.422
μV
1
0
000
00
000
-1/4LSB
-244.141
μV
0
1
111
11
111
-FS + 13/4LSB
-0.498291V
0
1
-Full Scale (-FS) + 3/4LSB
-0.499268V
0
NOTE:
10. The voltages listed above represent the ideal center of each output code shown with VREFIN =+2.5V.
-
+
-
CH
CS
CH
I/QIN+
VOUT+
VOUT-
I/QIN-
Φ1
Φ2
Φ1
FIGURE 15. ANALOG INPUT SAMPLE-AND-HOLD
HI5762
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