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參數(shù)資料
| 型號： | HI5767/2IA |
| 廠商： | Intersil |
| 文件頁數(shù)： | 7/15頁 |
| 文件大?。?/td> | 0K |
| 描述： | CONV A/D 10BIT 20MSPS 28-SOIC |
| 標(biāo)準(zhǔn)包裝： | 48 |
| 位數(shù)： | 10 |
| 采樣率（每秒）： | 20M |
| 數(shù)據(jù)接口： | 并聯(lián) |
| 轉(zhuǎn)換器數(shù)目： | 8 |
| 功率耗散（最大）： | 310mW |
| 電壓電源： | 模擬和數(shù)字 |
| 工作溫度： | -40°C ~ 85°C |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 28-SSOP（0.154"，3.90mm 寬） |
| 供應(yīng)商設(shè)備封裝： | 28-SSOP/QSOP |
| 包裝： | 管件 |
| 輸入數(shù)目和類型： | 2 個單端，單極；1 個差分，雙極 |
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notice. Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by Intersil is believed to be accurate and
reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result
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For information regarding Intersil Corporation and its products, see www.intersil.com
Video Definitions
Differential Gain and Differential Phase are two commonly
found video specifications for characterizing the distortion of
a chrominance signal as it is offset through the input voltage
range of an ADC.
Differential Gain (DG)
Differential Gain is the peak difference in chrominance
amplitude (in percent) relative to the reference burst.
Differential Phase (DP)
Differential Phase is the peak difference in chrominance
phase (in degrees) relative to the reference burst.
Timing Definitions
Refer to Figure 1 and Figure 2 for these definitions.
Aperture Delay (tAP)
Aperture delay is the time delay between the external
sample command (the falling edge of the clock) and the time
at which the signal is actually sampled. This delay is due to
internal clock path propagation delays.
Aperture Jitter (tAJ)
Aperture jitter is the RMS variation in the aperture delay due
to variation of internal clock path delays.
Data Hold Time (tH)
Data hold time is the time to where the previous data (N - 1)
is no longer valid.
Data Output Delay Time (tOD)
Data output delay time is the time to where the new data (N)
is valid.
Data Latency (tLAT)
After the analog sample is taken, the digital data representing
an analog input sample is output to the digital data bus on
the 7th cycle of the clock after the analog sample is taken.
This is due to the pipeline nature of the converter where the
analog sample has to ripple through the internal subconverter
stages. This delay is specified as the data latency. After the
data latency time, the digital data representing each
succeeding analog sample is output during the following
clock cycle. The digital data lags the analog input sample by 7
sample clock cycles.
Power-Up Initialization
This time is defined as the maximum number of clock cycles
that are required to initialize the converter at power-up. The
requirement arises from the need to initialize the dynamic
circuits within the converter.
HI5767
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| HI5767EVAL1 | 功能描述:數(shù)據(jù)轉(zhuǎn)換 IC 開發(fā)工具 HI5767 LW FREQUENCY EVALUATION PLATFORM RoHS:否 制造商:Texas Instruments 產(chǎn)品:Demonstration Kits 類型:ADC 工具用于評估:ADS130E08 接口類型:SPI 工作電源電壓:- 6 V to + 6 V |
| HI5767EVAL2 | 功能描述:數(shù)據(jù)轉(zhuǎn)換 IC 開發(fā)工具 HI5767 HI FREQUENCY EVALUATION PLATFORM RoHS:否 制造商:Texas Instruments 產(chǎn)品:Demonstration Kits 類型:ADC 工具用于評估:ADS130E08 接口類型:SPI 工作電源電壓:- 6 V to + 6 V |
| HI5780 | 制造商:INTERSIL 制造商全稱:Intersil Corporation 功能描述:10-Bit, 80 MSPS, High Speed, Low Power D/A Converter |
| HI5780-EV | 制造商:INTERSIL 制造商全稱:Intersil Corporation 功能描述:10-Bit, 80 MSPS, High Speed, Low Power D/A Converter |
| HI5780JCQ | 制造商:Rochester Electronics LLC 功能描述:32 PQFP COMTEMP VIDEO D/A 10BIT 80MHZ - Bulk 制造商:Harris Corporation 功能描述: |
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