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參數(shù)資料
| 型號(hào)： | HI7191IP |
| 廠商： | HARRIS SEMICONDUCTOR |
| 元件分類： | ADC |
| 英文描述： | 24-Bit, High Precision, Sigma Delta A/D Converter |
| 中文描述： | 1-CH 24-BIT DELTA-SIGMA ADC, SERIAL ACCESS, PDIP20 |
| 文件頁數(shù)： | 16/24頁 |
| 文件大?。?/td> | 187K |
| 代理商： | HI7191IP |
1912
The first combination is to reset both the BD and MSB bits
(BD = 0, MSB = 0). This sets up the interface for descending
byte order and MSB first format. When this combination is
used the user should always write the Instruction Register
such that the starting byte is the most significant byte address.
For example, read three bytes of DR starting with the most sig-
nificant byte. The first byte read will be the most significant in
MSB to LSB format. The next byte will be the next least signifi-
cant (recall descending byte order) again in MSB to LSB order.
The last byte will be the next lesser significant byte in MSB to
LSB order. The entire word was read MSB to LSB format.
The second combination is to set both the BD and MSB bits to
1. This sets up the interface for ascending byte order and LSB
first format. When this combination is used the user should
always write the Instruction Register such that the starting
byte is the least significant byte address. For example, read
three bytes of DR starting with the least significant byte. The
first byte read will be the least significant in LSB to MSB for-
mat. The next byte will be the next greater significant (recall
ascending byte order) again in LSB to MSB order. The last
byte will be the next greater significant byte in LSB to MSB
order. The entire word was read MSB to LSB format.
After completion of each communication cycle, The HI7191
interface enters a standby mode while waiting to receive a
new instruction byte.
Instruction Byte Phase
The instruction byte phase initiates a data transfer
sequence. The processor writes an 8-bit byte (Instruction
Byte) to the Instruction Register. The instruction byte informs
the HI7191 about the Data transfer phase activities and
includes the following information:
- Read or Write cycle
- Number of Bytes to be transferred
- Which register and starting byte to be accessed
Data Transfer Phase
In the data transfer phase, data transfer takes place as set
by the Instruction Register contents. See Write Operation
and Read Operation sections for detailed descriptions.
Instruction Register
The Instruction Register is an 8-bit register which is used
during a communications cycle for setting up read/write
operations.
R/W
- Bit 7 of the Instruction Register determines whether a
read or write operation will be done following the instruction
byte load. 0 = READ, 1 = WRITE.
MB1, MB0
- Bits 6 and 5 of the Instruction Register deter-
mine the number of bytes that will be accessed following the
instruction byte load. See Table 5 for the number of bytes to
transfer in the transfer cycle.
FSC
- Bit 4 is used to determine whether a Positive Full
Scale Calibration Register I/O transfer (FSC = 0) or a Nega-
tive Full Scale Calibration Register I/O transfer (FSC = 1) is
being performed (see Table 6).
A3, A2, A1, A0
- Bits 3 and 2 (A3 and A2) of the Instruction
Register determine which internal register will be accessed
while bits 1 and 0 (A1 and A0) determine which byte of that
register will be accessed first. See Table 6 for the address
decode.
INSTRUCTION
BYTE
DATA
BYTE 1
DATA
BYTE 2
DATA
BYTE 3
INSTRUCTION
CYCLE
DATA TRANSFER
CS
SDIO
FIGURE 13A. 2-WIRE, 3-BYTE READ OR WRITE TRANSFER
INSTRUCTION
BYTE
DATA
BYTE 1
DATA
BYTE 2
DATA
BYTE 3
INSTRUCTION
CYCLE
DATA TRANSFER
CS
SDIO
SDO
FIGURE 13B. 3-WIRE, 3-BYTE READ TRANSFER
INSTRUCTION REGISTER
MSB
6
5
4
3
2
1
LSB
R/W
MB1
MB0
FSC
A3
A2
A1
A0
TABLE 5. MULTIPLE BYTE ACCESS BITS
MB1
MB0
DESCRIPTION
0
0
Transfer 1 Byte
0
1
Transfer 2 Bytes
1
0
Transfer 3 Bytes
1
1
Transfer 4 Bytes
HI7191
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