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參數(shù)資料
| 型號(hào)： | HIP6500EVAL1 |
| 廠商： | Intersil Corporation |
| 元件分類： | 基準(zhǔn)電壓源/電流源 |
| 英文描述： | Multiple Linear Power Controller with ACPI Control Interface |
| 中文描述： | 多重線性電源控制器ACPI控制接口 |
| 文件頁數(shù)： | 8/15頁 |
| 文件大?。?/td> | 155K |
| 代理商： | HIP6500EVAL1 |
8
Functional Timing Diagrams
Figures 4 through 8 are timing diagrams, detailing the power
up/down sequences of all three outputs in response to the
status of the enable (EN3VDL, EN5VDL) and sleep-state
pins (S3, S5), as well as the status of the ATX supply.
The status of the EN3VDL and EN5VDL pins can only be
changed while in active (S0, S1) states, when the bias
supply (5VSB pin) is below POR level, or during chip
shutdown (SS pin shorted to GND); a status change of these
two pins while in a sleep state is ignored.
Not shown in these diagrams is the deglitching feature used
to protect against false sleep state tripping. Both S3 and S5
pins are protected against noise by a 2
μ
s filter (typically 1 -
4
μ
s). This feature is useful in noisy computer environments if
the control signals have to travel over significant distances.
Additionally, the S3 pin features a 200
μ
s delay in
transitioning to sleep states. Once the S3 pin goes low, an
internal timer is activated. At the end of the 200
μ
s interval, if
the S5 pin is low, the HIP6500 switches into S5 sleep state; if
the S5 pin is high, the HIP6500 goes into S3 sleep state.
FIGURE 4. 3V
DUAL
AND 5V
DUAL
TIMING DIAGRAM FOR
EN3VDL = 1, EN5VDL = 1
5VSB
12V
S3
S5
5VDLSB
DLA
3V3DLSB
3V3DL
5VDL
FIGURE 5. 3V
DUAL
AND 5V
DUAL
TIMING DIAGRAM FOR
EN3VDL = 1, EN5VDL = 0
5VSB
12V
S3
S5
5VDLSB
DLA
3V3DLSB
3V3DL
5VDL
FIGURE 6. 3V
DUAL
AND 5V
DUAL
TIMING DIAGRAM FOR
EN3VDL = 0, EN5VDL = 1
5VSB
12V
S3
S5
5VDLSB
DLA
3V3DLSB
3V3DL
5VDL
FIGURE 7. 3V
DUAL
AND 5V
DUAL
TIMING DIAGRAM FOR
EN3VDL = 0, EN5VDL = 0
5VSB
12V
S3
S5
5VDLSB
DLA
3V3DLSB
3V3DL
5VDL
HIP6500
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| HIP6501 | Triple Linear Power Controller with ACPI Control Interface |
| HIP6501A | Triple Linear Power Controller with ACPI Control Interface(帶ACPI控制接口的線性電源控制器) |
| HIP6501EVAL1 | Triple Linear Power Controller with ACPI Control Interface |
| HIP6501ACB | Triple Linear Power Controller with ACPI Control Interface |
| HIP6521 | PWM and Triple Linear Power Controller |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| HIP6501 | 制造商:INTERSIL 制造商全稱:Intersil Corporation 功能描述:Triple Linear Power Controller with ACPI Control Interface |
| HIP6501A | 制造商:INTERSIL 制造商全稱:Intersil Corporation 功能描述:Triple Linear Power Controller with ACPI Control Interface |
| HIP6501A_04 | 制造商:INTERSIL 制造商全稱:Intersil Corporation 功能描述:Triple Linear Power Controller with ACPI Control Interface |
| HIP6501ACB | 功能描述:IC PWM TRIPLE POWER CTRLR 16SOIC RoHS:否 類別:集成電路 (IC) >> PMIC - 電源控制器，監(jiān)視器 系列:- 產(chǎn)品培訓(xùn)模塊:Lead (SnPb) Finish for COTS Obsolescence Mitigation Program 標(biāo)準(zhǔn)包裝:2,500 系列:- 應(yīng)用:多相控制器 輸入電壓:- 電源電壓:9 V ~ 14 V 電流 - 電源:- 工作溫度:-40°C ~ 85°C 安裝類型:表面貼裝 封裝/外殼:40-WFQFN 裸露焊盤 供應(yīng)商設(shè)備封裝:40-TQFN-EP（5x5） 包裝:帶卷 (TR) |
| HIP6501ACB-T | 功能描述:IC PWM TRIPLE POWER CTRLR 16SOIC RoHS:否 類別:集成電路 (IC) >> PMIC - 電源控制器，監(jiān)視器 系列:- 產(chǎn)品培訓(xùn)模塊:Lead (SnPb) Finish for COTS Obsolescence Mitigation Program 標(biāo)準(zhǔn)包裝:2,500 系列:- 應(yīng)用:多相控制器 輸入電壓:- 電源電壓:9 V ~ 14 V 電流 - 電源:- 工作溫度:-40°C ~ 85°C 安裝類型:表面貼裝 封裝/外殼:40-WFQFN 裸露焊盤 供應(yīng)商設(shè)備封裝:40-TQFN-EP（5x5） 包裝:帶卷 (TR) |
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