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參數(shù)資料
| 型號： | HIP7038A8 |
| 廠商： | Intersil Corporation |
| 英文描述： | J1850 8-Bit 68HC05 Microcontroller 8K EEPROM Version |
| 中文描述： | J1850 8位微控制器8K的EEPROM的68HC05的版本 |
| 文件頁數(shù)： | 4/5頁 |
| 文件大?。?/td> | 21K |
| 代理商： | HIP7038A8 |
9-102
HIP7038A8
Functional Description
The HIP7038A8 MCU is functionally identical to the
HIP7030A2 and HIP7030A8 microcontrollers. The device
differs only in that the on-board masked ROM has been
replaced with EEPROM, which allows the device to be
rapidly programmed by the user. For detailed information
about the functions included on the HIP7038A8 refer to File
Number 3646, the technical specification of the HIP7030A2
Microcontroller. Only differences are presented here.
The availability of the HIP7038A8 dramatically reduces the
time-to-market of new products by providing the develop-
ment engineer rapid feedback during the design phase of a
HIP7030A2/8 project.
The EEPROM is reusable and can be reprogrammed up to
10
4
times.
Memory Organization
The HIP7038A8 MCU addresses 8192 bytes of memory and
I/O registers with its program counter. Of these locations,
8184 have been implemented as shown in Figure 1. The first
256 bytes of memory (page zero) include: 24 bytes of I/O
features such as data ports, the port DDRs, Timer, serial
peripheral interface (SPI), and J1850 VPW Registers; 48
bytes of user ROM, and 176 bytes of RAM. The next 7680
bytes complete the user ROM. The Built-In-Test ROM (242
bytes) is contained in memory locations $1F00 through
$1FF1. The 14 highest address bytes contain the user
defined reset and the interrupt vectors. Eight bytes of the
lowest 32 memory locations are unused and the 176 bytes of
user RAM include up to 64 bytes for the stack. Since most
programs use only a small part of the allocated stack loca-
tions for interrupts and/or subroutine stacking purposes, the
unused bytes are usable for program data storage.
NOTE: Accessable in test mode only.
FIGURE 1. MEMORY MAP OF THE HIP7038A8
14 BYTES
VECTORS
USER
VECTORS
BUILT-IN-TEST
32 BYTES
I/O
48 BYTES
ROM
USER
176 BYTES
RAM
7680 BYTES
ROM
USER
64 BYTES
STACK
BUILT-IN-TEST
$1FF2
$1FF1
$1FE2
$1FE1
$1F00
$1EFF
$0100
$00FF
$00C0
$00BF
$0050
$004F
$0020
$001F
$1FFF
$0000
10 BYTES
TIMER
2 BYTES
1 BYTE
1 BYTE
TEST
UNUSED
UNUSED
WATCHDOG
2 BYTES
3 BYTES
INTERFACE
3 BYTES
SENDEC
INTERFACE
SERIAL PERIPHERAL
2 BYTES
1 BYTE
2 BYTES
UNUSED
UNUSED
UNUSED
2 BYTES
2 BYTES
1 BYTE
PORTS
PORTS
PORTS
$1F
$1E
$1D
$1C
$1B
$1A
$19
$18
$17
$16
$15
$14
$13
$12
$11
$10
$0F
$0E
$0D
$0C
$0B
$0A
$09
$08
$07
$06
$05
$04
$03
$02
$01
$00
TEST REGISTER
(SEE NOTE)
UNUSED
ALTERNATE COUNTER HIGH REGISTER
INPUT CAPTURE HIGH REGISTER
SENDEC CONTROL REGISTER
UNUSED
UNUSED
SERIAL PERIPHERAL CONTROL REGISTER
UNUSED
PORT D SPECIAL FUNCTION REGISTER
UNUSED
UNUSED
UNUSED
UNUSED
PORT A DATA DIRECTION REGISTER
PORT D DATA REGISTER
PORT A DATA REGISTER
0032
0031
0192
0191
0256
0255
7936
7935
8178
8177
8191
BYTES
256
0000
0000
0031
0080
0079
PORT D DATA DIRECTION REGISTER
SERIAL PERIPHERAL STATUS REGISTER
SERIAL PERIPHERAL DATA I/O REGISTER
SENDEC STATUS REGISTER
SENDEC DATA REGISTER
TIMER CONTROL REGISTER
TIMER STATUS REGISTER
INPUT CAPTURE LOW REGISTER
OUTPUT COMPARE HIGH REGISTER
OUTPUT COMPARE LOW REGISTER
COUNTER HIGH REGISTER
COUNTER LOW REGISTER
ALTERNATE COUNTER LOW REGISTER
WATCHDOG RESET REGISTER
WATCHDOG STATUS REGISTER
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