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參數資料
| 型號： | HM1-6514-9 |
| 廠商： | INTERSIL CORP |
| 元件分類： | SRAM |
| 英文描述： | 1024 x 4 CMOS RAM |
| 中文描述： | 1K X 4 STANDARD SRAM, 320 ns, CDIP18 |
| 封裝： | CERAMIC, DIP-18 |
| 文件頁數： | 1/7頁 |
| 文件大小： | 41K |
| 代理商： | HM1-6514-9 |
6-1
March 1997
HM-6514
1024 x 4 CMOS RAM
Features
Low Power Standby. . . . . . . . . . . . . . . . . . . 125
μ
W Max
Low Power Operation . . . . . . . . . . . . . 35mW/MHz Max
Data Retention . . . . . . . . . . . . . . . . . . . . . . . at 2.0V Min
TTL Compatible Input/Output
Common Data Input/Output
Three-State Output
Standard JEDEC Pinout
Fast Access Time. . . . . . . . . . . . . . . . . . 120/200ns Max
18 Pin Package for High Density
On-Chip Address Register
Gated Inputs - No Pull Up or Pull Down Resistors
Required
Description
The HM-6514 is a 1024 x 4 static CMOS RAM fabricated
using self-aligned silicon gate technology. The device utilizes
synchronous circuitry to achieve high performance and low
power operation.
On-chip latches are provided for addresses allowing efficient
interfacing with microprocessor systems. The data output
can be forced to a high impedance state for use in expanded
memory arrays.
Gated inputs allow lower operating current and also elimi-
nate the need for pull up or pull down resistors. The
HM-6514 is a fully static RAM and may be maintained in any
state for an indefinite period of time.
Data retention supply voltage and supply current are guaran-
teed over temperature.
Ordering Information
120ns
200ns
300ns
TEMPERATURE RANGE
-40
o
C to +85
o
C
-40
o
C to +85
o
C
PACKAGE
PKG. NO.
HM3-6514S-9
HM3-6514B-9
HM3-6514-9
PDIP
E18.3
HM1-6514S-9
HM1-6514B-9
HM1-6514-9
CERDIP
F18.3
24502BVA
-
-
-
JAN#
F18.3
8102402VA
8102404VA
8102406VA
-
SMD#
F18.3
-
-
-
-40
o
C to +85
o
C
-55
o
C to +125
o
C
CLCC
J18.B
-
-
HM4-6514-B
J18.B
Pinouts
HM-6514 (PDIP, CERDIP)
TOP VIEW
HM-6514 (CLCC)
TOP VIEW
10
11
12
13
14
15
16
17
18
9
8
7
6
5
4
3
2
1
V
CC
A8
A9
DQ0
DQ1
DQ2
DQ3
A7
W
A6
A5
A4
A3
A0
A1
E
A2
GND
PIN
DESCRIPTION
A
Address Input
E
Chip Enable
W
Write Enable
D
Data Input
Q
Data Output
3
4
5
6
7
8
9
10
11
2
1
17
13
12
16
15
14
A3
A4
A0
A1
A2
G
D
W
E
A
A
DQ0
DQ1
A9
DQ2
A8
A
V
C
18
File Number
2995.1
CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.
http://www.intersil.com or 407-727-9207
|
Copyright
Intersil Corporation 1999
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