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參數(shù)資料
| 型號： | HM1-6516-9 |
| 廠商： | INTERSIL CORP |
| 元件分類： | SRAM |
| 英文描述： | 2K x 8 CMOS RAM |
| 中文描述： | 2K X 8 STANDARD SRAM, 200 ns, CDIP24 |
| 封裝： | CERAMIC, DIP-24 |
| 文件頁數(shù)： | 5/6頁 |
| 文件大小： | 31K |
| 代理商： | HM1-6516-9 |
6-5
Timing Waveforms
The address information is latched in the on-chip registers
on the falling edge of E (T = 0), minimum address setup and
hold time requirements must be met. After the required hold
time, the addresses may change state without affecting
device operation. During time (T = 1), the outputs become
enabled but data is not valid until time (T = 2), W must
remain high throughout the read cycle. After the data has
been read, E may return high (T = 3). This will force the out-
put buffers into a high impedance mode at time (T = 4). G is
used to disable the output buffers when in a logical “1” state
(T = -1, 0, 3, 4, 5). After (T = 4) time, the memory is ready for
the next cycle.
Timing Waveforms
(Continued)
HIGH
NEXT
(11)
TAVEL
(12)
TELAX
ADD
(5)
TEHQZ
VALID DATA OUT
(5)
TEHQZ
(8)
TGHQZ
(7)
TGLQX
A
E
W
DQ
G
TIME
REFERENCE
-1
0
1
2
3
4
5
TAVQV
(2)
(11)
TAVEL
(18)
TELEL
(9)
TELEH
(10)
TEHEL
(10)
TEHEL
TELQV
(1)
TELQX
(3)
TGLQV
(6)
FIGURE 1. READ CYCLE
VALID ADD
(11)
TAVEL
(12)
TELAX
(11)
TAVEL
(17)
TWHDX
HIGH
VALID DATA IN
A
E
W
DQ
G
TIME
REFERENCE
-1
0
1
2
3
4
5
VALID ADD
NEXT ADD
(18)
TELEL
(10)
TEHEL
(10)
TEHEL
(9)
TELEH
(13)
TWLWH
(14)
TWLEH
(16)
TDVWH
FIGURE 2. WRITE CYCLE
(15)
TELWH
HM-6516
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| HM1-6516-9 WAF | 制造商:Harris Corporation 功能描述: |
| HM1-6516B | 制造商:Rochester Electronics LLC 功能描述:- Bulk |
| HM1-6516B/883 | 制造商:Rochester Electronics LLC 功能描述:MIL STD 2048 X 8 CMOS RAM 120NS ACC TIME 24 PIN CERDIP - Bulk |
| HM1-6516B3396-101 | 制造商:Harris Corporation 功能描述: |
| HM1-6516B-9 | 制造商:Rochester Electronics LLC 功能描述:- Bulk |
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