- 您現(xiàn)在的位置：買賣IC網(wǎng) > PDF目錄371831 > HM4-6516-9 (HARRIS SEMICONDUCTOR) 2K x 8 CMOS RAM PDF資料下載
參數(shù)資料
| 型號(hào)： | HM4-6516-9 |
| 廠商： | HARRIS SEMICONDUCTOR |
| 元件分類： | DRAM |
| 英文描述： | 2K x 8 CMOS RAM |
| 中文描述： | 2K X 8 STANDARD SRAM, 200 ns, CQCC32 |
| 文件頁數(shù)： | 6/6頁 |
| 文件大?。?/td> | 31K |
| 代理商： | HM4-6516-9 |
6-6
All Intersil semiconductor products are manufactured, assembled and tested under
ISO9000
quality systems certification.
Intersil products are sold by description only. Intersil Corporation reserves the right to make changes in circuit design and/or specifications at any time without
notice. Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by Intersil is believed to be accurate
and reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which
may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Intersil or its subsidiaries.
For information regarding Intersil Corporation and its products, see web site
http://www.intersil.com
Sales Office Headquarters
NORTH AMERICA
Intersil Corporation
P. O. Box 883, Mail Stop 53-204
Melbourne, FL 32902
TEL: (407) 724-7000
FAX: (407) 724-7240
TEL: (32) 2.724.2111
FAX: (32) 2.724.22.05
EUROPE
Intersil SA
Mercure Center
100, Rue de la Fusee
1130 Brussels, Belgium
ASIA
Intersil (Taiwan) Ltd.
Taiwan Limited
7F-6, No. 101 Fu Hsing North Road
Taipei, Taiwan
Republic of China
TEL: (886) 2 2716 9310
FAX: (886) 2 2715 3029
The write cycle is initiated on the falling edge of E (T = 0),
which latches the address information in the on-chip
registers. If a write cycle is to be performed where the output
is not to become active, G can be held high (inactive).
TDVWH and TWHDX must be met for proper device opera-
tion regardless of G. If E and G fall before W falls (read
mode), a possible bus conflict may exist. If E rises before W
rises, reference data setup and hold times to the E rising
edge. The write operation is terminated by the first rising edge
of W (T = 2) or E (T = 3). After the minimum E high time
(TEHEL), the next cycle may begin. If a series of consecutive
write cycles are to be performed, the W line may be held low
until all desired locations have been written. In this case, data
setup and hold times must be referenced to the rising of E.
Typical Performance Curve
-55
-35
-15
5
25
45
65
85
105
125
-12
-11
-10
-9
-8
-7
-6
-5
-4
-3
V
CC
= 2.0V
L
C
/
FIGURE 3. TYPICAL ICCDR vs T
A
HM-6516
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| HM1-65162-9 | 2K x 8 Asynchronous CMOS Static RAM |
| HM1-65162B-9 | 2K x 8 Asynchronous CMOS Static RAM |
| HM1-65162C-9 | 2K x 8 Asynchronous CMOS Static RAM |
| HM-65162 | 2K x 8 Asynchronous CMOS Static RAM |
| HM-65162883 | 2K x 8 Asynchronous CMOS Static RAM |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| HM4-6516B | 制造商:Rochester Electronics LLC 功能描述:- Bulk 制造商:Harris Corporation 功能描述: |
| HM4-6516B/883 | 制造商:Rochester Electronics LLC 功能描述:- Bulk |
| HM4-6516-B/883 | 制造商:Rochester Electronics LLC 功能描述:- Bulk |
| HM4-6516B3280-003 | 制造商:Rochester Electronics LLC 功能描述:- Bulk |
| HM4-6516B-8 | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:x8 SRAM |
發(fā)布緊急采購，3分鐘左右您將得到回復(fù)。