參數(shù)資料
型號(hào)： HM5116100S-7
廠商： Hitachi,Ltd.
英文描述： 16M FP DRAM (16-Mword x 1-bit) 4k Refresh
中文描述： 1,600計(jì)劃生育的DRAM（16 Mword × 1位）4K的刷新
文件頁(yè)數(shù)： 10/24頁(yè)
文件大小： 217K
代理商： HM5116100S-7
HM5116100 Series
10
Notes: 1. AC measurements assume t
T
= 5 ns.
2. An initial pause of 200
μ
s is required after power up followed by a minimum of eight initialization
cycles (any combination of cycles containing
RAS
-only refresh or
CAS
-before-
RAS
refresh). If
the internal refresh counter is used, a minimum of eight
CAS
-before-
RAS
refresh cycles are
required.
3. Operation with the t
(max) limit insures that t
(max) can be met, t
(max) is specified as a
reference point only; if t
is greater than the specified t
RCD
(max) limit, then access time is
controlled exclusively by t
CAC
.
4. Operation with the t
(max) limit insures that t
(max) can be met, t
(max) is specified as a
reference point only; if t
is greater than the specified t
RAD
(max) limit, then access time is
controlled exclusively by t
AA
.
5. V
(min) and V
(max) are reference levels for measuring timing of input signals. Also, transition
times are measured between V
IH
(min) and V
IL
(max).
6. Assume that t
≤
t
(max) and t
≤
t
RAD
(max). If t
or t
is greater than the maximum
recommended value shown in this table, t
RAC
exceeds the value shown.
7. Measured with a load circuit equivalent to 2 TTL loads and 100 pF.
8. Assume that t
RCD
≥
t
RCD
(max) and t
RAD
≤
t
RAD
(max).
9. Assume that t
RCD
≤
t
RCD
(max) and t
RAD
≥
t
RAD
(max).
10.Either t
RCH
or t
RRH
must be satisfied for a read cycles.
11.t
(max) and t
(max) define the time at which the outputs achieve the open circuit condition
and are not referred to output voltage levels.
12.t
, t
, t
, t
and t
are not restrictive operating parameters. They are included in the
data sheet as electrical characteristics only; if t
≥
t
(min), the cycle is an early write cycle
and the data out pin will remain open circuit (high impedance) throughout the entire cycle; if t
RWD
≥
t
RWD
(min), t
≥
t
(min), and t
≥
t
(min), or t
≥
t
(min), t
≥
t
(min) and t
CPW
≥
t
(min), the cycle is a read-modify-write and the data output will contain data read from the
selected cell; if neither of the above sets of conditions is satisfied, the condition of the data out
(at access time) is indeterminate.
13.These parameters are referenced to
CAS
leading edge in early write cycles and to
WE
leading
edge in delayed write or read-modify-write cycles.
14.t
RASP
defines
RAS
pulse width in fast page mode cycles.
15.Access time is determined by the longest among t
AA
, t
CAC
and t
CPA
.
16.The 16M DRAM offers a 16-bit time saving parallel test mode. Address CA0, CA1, CA10 and
CA11 for the 16M
×
1 are don’t care during test mode. Test mode is set by performing a
WE
-
and-
CAS
-before-
RAS
(WCBR) cycle. In 16-bit parallel test mode, data is written into 16 bits in
parallel at Din and read out from Dout.
If 16 bits are equal (all 1s or 0s), data output pin is a high state during test mode read cycle, then
the device has passed. If they are not equal, data output pin is a low state, then the device has
failed. Refresh during test mode operation can be performed by normal read cycles or by WCBR
refresh cycles.
To get out of test mode and enter a normal operation mode, perform either a regular
CAS
-
before-
RAS
refresh cycle or
RAS
-only refresh cycle.
17.In a test mode read cycle, the value of t
, t
, t
and t
is delayed by 2 ns to 5 ns for the
specified value. These parameters should be specified in test mode cycles by adding the above
value to the specified value in this data sheet.
18.XXX: H or L (H: V
IH
(min)
≤
V
IN
≤
V
IH
(max), L: V
IL
(min)
≤
V
IN
≤
V
IL
(max))
///////: Invalid Dout
相關(guān)PDF資料
PDF描述
HM5117805J-5 16M EDO DRAM(2-Mword*8-bit) 2k Refresh
HM5117805J-6 16M EDO DRAM(2-Mword*8-bit) 2k Refresh
HM5117805J-7 16 M EDO DRAM(2-Mword*8-bit) 2 k Refresh
HM5117805LJ-5 16 M EDO DRAM (2-Mword X 8-bit) 2 k Refresh
HM5117805LS-5 16 M EDO DRAM (2-Mword X 8-bit) 2 k Refresh
相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
HM5116100Z-10 制造商:未知廠家 制造商全稱:未知廠家 功能描述:x1 Fast Page Mode DRAM
HM5116100Z-6 制造商:未知廠家 制造商全稱:未知廠家 功能描述:x1 Fast Page Mode DRAM
HM5116100Z-7 制造商:未知廠家 制造商全稱:未知廠家 功能描述:x1 Fast Page Mode DRAM
HM5116100Z-8 制造商:未知廠家 制造商全稱:未知廠家 功能描述:x1 Fast Page Mode DRAM
HM5116160J-5 制造商:HITACHI 制造商全稱:Hitachi Semiconductor 功能描述:1048576-word x 16-bit Dynamic RAM
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