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參數(shù)資料
| 型號： | HM51S4260CLJ-8 |
| 廠商： | Hitachi,Ltd. |
| 英文描述： | 262,144-word x 16-bit Dynamic Random Access Memory |
| 中文描述： | 262,144字× 16位動態(tài)隨機存取存儲器 |
| 文件頁數(shù)： | 13/27頁 |
| 文件大?。?/td> | 260K |
| 代理商： | HM51S4260CLJ-8 |
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HM514260C, HM51S4260C Series
13
22.t
CPN
and t
CP
are determined by the time that both
UCAS
and
LCAS
are high.
23.When output buffers are enabled once, sustain the low impedance state until valid data is obtained.
When output buffer is turned on and off within a very short time, generally it causes large V
CC
/V
SS
line noise, which causes to degrade V
IH
min/V
IL
max level.
24.If you use distributed CBR refresh mode with 15.6
μ
s interval in normal read/write cycle, CBR
refresh should be executed within 15.6
μ
s immediately after exiting from and before entering
into self refresh mode.
25.If you use
RAS
only refresh or CBR burst refresh mode in normal read/write cycle, 512 cycles
of distributed CBR refresh with 15.6
μ
s interval should be executed within 8 ms immediately
after exiting from and before entering into the self refresh mode.
refresh mode, all memory cells need to be refreshed before re-entering the self refresh mode
again.
27.
H or L (H: V
IH
(min)
≤
V
IN
≤
V
IH
(max)
,
L: V
IL
(min)
≤
V
IN
≤
V
IL
(max))
Invalid Dout
@
à
@
à
@
à
@
à
@
à
相關PDF資料 |
PDF描述 |
|---|---|
| HM514260CLTT-6 | 262,144-word x 16-bit Dynamic Random Access Memory |
| HM514260CLTT-6R | 262,144-word x 16-bit Dynamic Random Access Memory |
| HM514260CLTT-7 | 262,144-word x 16-bit Dynamic Random Access Memory |
| HM514260CLTT-8 | 262,144-word x 16-bit Dynamic Random Access Memory |
| HM514260CTT-6 | 262,144-word x 16-bit Dynamic Random Access Memory |
相關代理商/技術參數(shù) |
參數(shù)描述 |
|---|---|
| HM51W17805J-6GS | 制造商:Hitachi 功能描述: |
| HM51W18160CLTT-6 | 制造商:Renesas Electronics Corporation 功能描述: |
| HM51W18165LTT6 | 制造商:HITACHI 功能描述:* |
| HM51W4260CLTT-6 | 制造商:Hitachi 功能描述: |
| HM5212165/2805 | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:Series 128M LVTTL Interface SDRAM 66 MHz 2-Mword X 16-Bit X4-Bank |
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