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參數(shù)資料
| 型號(hào)： | HM5225405B |
| 廠商： | Hitachi,Ltd. |
| 英文描述： | 256M LVTTL interface SDRAM(256M LVTTL接口同步DRAM) |
| 中文描述： | 256M LVTTL接口的SDRAM（256M LVTTL接口同步的DRAM） |
| 文件頁數(shù)： | 17/64頁 |
| 文件大?。?/td> | 802K |
| 代理商： | HM5225405B |
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HM5225165B/HM5225805B/HM5225405B-75/A6/B6
17
From PRECHARGE state, command operation
To [DESL], [NOP]:
When these commands are executed, the SDRAM enters the IDLE state after t
RP
has
elapsed from the completion of precharge.
From IDLE state, command operation
To [DESL], [NOP], [PRE] or [PALL]:
These commands result in no operation.
To [ACTV]:
The bank specified by the address pins and the ROW address is activated.
To [REF], [SELF]:
The SDRAM enters refresh mode (auto-refresh or self-refresh).
To [MRS]:
The synchronous DRAM enters the mode register set cycle.
From ROW ACTIVE state, command operation
To [DESL], [NOP]:
These commands result in no operation.
To [READ], [READ A]:
A read operation starts. (However, an interval of t
RCD
is required.)
To [WRIT], [WRIT A]:
A write operation starts. (However, an interval of t
RCD
is required.)
To [ACTV]:
This command makes the other bank active. (However, an interval of t
RRD
is required.)
Attempting to make the currently active bank active results in an illegal command.
To [PRE], [PALL]:
These commands set the SDRAM to precharge mode. (However, an interval of t
RAS
is
required.)
From READ state, command operation
To [DESL], [NOP]:
These commands continue read operations until the burst operation is completed.
To [READ], [READ A]:
Data output by the previous read command continues to be output. After
CAS
latency, the data output resulting from the next command will start.
To [WRIT], [WRIT A]:
These commands stop a burst read, and start a write cycle.
To [ACTV]:
This command makes other banks bank active. (However, an interval of t
RRD
is required.)
Attempting to make the currently active bank active results in an illegal command.
To [PRE], [PALL]:
These commands stop a burst read, and the SDRAM enters precharge mode.
From READ with AUTO-PRECHARGE state, command operation
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PDF描述 |
|---|---|
| HM5225805B | 256M LVTTL interface SDRAM(256M LVTTL接口同步DRAM) |
| HM5225165B | 256M LVTTL interface SDRAM(256M LVTTL接口同步DRAM) |
| HM5251405B | 512-Mbit SDRAM(512M位同步RAM) |
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| HM5225405B-75 | 制造商:ELPIDA 制造商全稱:Elpida Memory 功能描述:256M LVTTL interface SDRAM 133 MHz/100 MHz 4-Mword 】 16-bit 】 4-bank/8-Mword 】 8-bit 】 4-bank /16-Mword 】 4-bit 】 4-bank PC/133, PC/100 SDRAM |
| HM5225405B-A6 | 制造商:ELPIDA 制造商全稱:Elpida Memory 功能描述:256M LVTTL interface SDRAM 133 MHz/100 MHz 4-Mword 】 16-bit 】 4-bank/8-Mword 】 8-bit 】 4-bank /16-Mword 】 4-bit 】 4-bank PC/133, PC/100 SDRAM |
| HM5225405B-B6 | 制造商:ELPIDA 制造商全稱:Elpida Memory 功能描述:256M LVTTL interface SDRAM 133 MHz/100 MHz 4-Mword 】 16-bit 】 4-bank/8-Mword 】 8-bit 】 4-bank /16-Mword 】 4-bit 】 4-bank PC/133, PC/100 SDRAM |
| HM5225405BLTT-75 | 制造商:ELPIDA 制造商全稱:Elpida Memory 功能描述:256M LVTTL interface SDRAM 133 MHz/100 MHz 4-Mword 】 16-bit 】 4-bank/8-Mword 】 8-bit 】 4-bank /16-Mword 】 4-bit 】 4-bank PC/133, PC/100 SDRAM |
| HM5225405BLTT-A6 | 制造商:ELPIDA 制造商全稱:Elpida Memory 功能描述:256M LVTTL interface SDRAM 133 MHz/100 MHz 4-Mword 】 16-bit 】 4-bank/8-Mword 】 8-bit 】 4-bank /16-Mword 】 4-bit 】 4-bank PC/133, PC/100 SDRAM |
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