- 您現(xiàn)在的位置：買賣IC網(wǎng) > PDF目錄370621 > HM5264165D (Hitachi,Ltd.) 64M LVTTL interface SDRAM(64M LVTTL接口同步DRAM) PDF資料下載
參數(shù)資料
| 型號： | HM5264165D |
| 廠商： | Hitachi,Ltd. |
| 英文描述： | 64M LVTTL interface SDRAM(64M LVTTL接口同步DRAM) |
| 中文描述： | 6400 LVTTL接口的SDRAM（6400 LVTTL接口同步的DRAM） |
| 文件頁數(shù)： | 22/67頁 |
| 文件大?。?/td> | 615K |
| 代理商： | HM5264165D |
第1頁第2頁第3頁第4頁第5頁第6頁第7頁第8頁第9頁第10頁第11頁第12頁第13頁第14頁第15頁第16頁第17頁第18頁第19頁第20頁第21頁當(dāng)前第22頁第23頁第24頁第25頁第26頁第27頁第28頁第29頁第30頁第31頁第32頁第33頁第34頁第35頁第36頁第37頁第38頁第39頁第40頁第41頁第42頁第43頁第44頁第45頁第46頁第47頁第48頁第49頁第50頁第51頁第52頁第53頁第54頁第55頁第56頁第57頁第58頁第59頁第60頁第61頁第62頁第63頁第64頁第65頁第66頁第67頁
HM5264165D-A60, HM5264805D-A60, HM5264405D-A60
22
Operation of the SDRAM
Read/Write Operations
Bank active:
Before executing a read or write operation, the corresponding bank and the row address must
be activated by the bank active (ACTV) command. Bank 0, bank 1, bank 2 or bank 3 is activated according
to the status of the A12/A13 pin, and the row address (AX0 to AX11) is activated by the A0 to A11 pins at
the bank active command cycle. An interval of t
RCD
is required between the bank active command input
and the following read/write command input.
Read operation:
A read operation starts when a read command is input. Output buffer becomes Low-Z in
the (
CAS
Latency - 1) cycle after read command set. HM5264165D, HM5264805D series, HM5264405D
can perform a burst read operation.
The burst length can be set to 1, 2, 4, 8 or full-page (256; HM5264165D, 512; HM5264805D, 1024;
HM5264405D). The start address for a burst read is specified by the column address (AY0 to AY7;
HM5264165D, AY0 to AY8; HM5264805D, AY0 to AY9; HM5264405D) and the bank select address
(A12/A13) at the read command set cycle. In a read operation, data output starts after the number of clocks
specified by the
CAS
Latency. The
CAS
Latency can be set to 2 or 3.
When the burst length is 1, 2, 4, 8, the Dout buffer automatically becomes High-Z at the next clock after
the successive burst-length data has been output.
The
CAS
latency and burst length must be specified at the mode register.
CAS
Latency
READ
CLK
Command
Dout
ACTV
Row
Column
Address
CL = 2
CL = 3
out 0
out 1
out 2
out 3
out 0
out 1
out 2
out 3
t
RCD
CL =
CAS
latency
Burst Length = 4
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| HM5264805D | 64M LVTTL interface SDRAM(64M LVTTL接口同步DRAM) |
| HM5264405F | 64M LVTTL interface SDRAM(64M LVTTL接口同步DRAM) |
| HM5264805F-75 | Circular Connector; MIL SPEC:MIL-C-26482, Series I, Solder; Body Material:Aluminum; Series:PT06; No. of Contacts:36; Connector Shell Size:22; Connecting Termination:Solder; Circular Shell Style:Straight Plug; Body Style:Straight |
| HM5264805F-A60 | Circular Connector; MIL SPEC:MIL-C-26482, Series I, Solder; Body Material:Aluminum; Series:PT06; No. of Contacts:36; Connector Shell Size:22; Connecting Termination:Solder; Circular Shell Style:Straight Plug; Body Style:Straight |
| HM5264805F-B60 | Circular Connector; MIL SPEC:MIL-C-26482, Series I, Solder; Body Material:Aluminum; Series:PT06; Number of Contacts:36; Connector Shell Size:22; Connecting Termination:Solder; Circular Shell Style:Straight Plug; Body Style:Straight |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| HM5264165D-B60/4805D-B60/4405D-B60 | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:64M LVTTL Interface SDRAM 100 MHz 1-Mword X 1 |
| HM5264165DLTT-80 | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:x16 SDRAM |
| HM5264165DLTT-B60 | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:x16 SDRAM |
| HM5264165DTT-80 | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:x16 SDRAM |
| HM5264165DTT-B60 | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:x16 SDRAM |
發(fā)布緊急采購，3分鐘左右您將得到回復(fù)。