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參數(shù)資料
| 型號： | HM5264805D |
| 廠商： | Hitachi,Ltd. |
| 英文描述： | 64M LVTTL interface SDRAM(64M LVTTL接口同步DRAM) |
| 中文描述： | 6400 LVTTL接口的SDRAM（6400 LVTTL接口同步的DRAM） |
| 文件頁數(shù)： | 41/67頁 |
| 文件大?。?/td> | 615K |
| 代理商： | HM5264805D |
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HM5264165D-A60, HM5264805D-A60, HM5264405D-A60
41
Refresh
Auto-refresh:
All the banks must be precharged before executing an auto-refresh command. Since the
auto-refresh command updates the internal counter every time it is executed and determines the banks and
the ROW addresses to be refreshed, external address specification is not required. The refresh cycle is
4096 cycles/64 ms. (4096 cycles are required to refresh all the ROW addresses.) The output buffer
becomes High-Z after auto-refresh start. In addition, since a precharge has been completed by an internal
operation after the auto-refresh, an additional precharge operation by the precharge command is not
required.
Self-refresh:
After executing a self-refresh command, the self-refresh operation continues while CKE is
held Low. During self-refresh operation, all ROW addresses are refreshed by the internal refresh timer. A
self-refresh is terminated by a self-refresh exit command. Before and after self-refresh mode, execute auto-
refresh to all refresh addresses in or within 64 ms period on the condition (1) and (2) below.
(1) Enter self-refresh mode within 15.6
μ
s after either burst refresh or distributed refresh at equal interval
to all refresh addresses are completed.
(2) Start burst refresh or distributed refresh at equal interval to all refresh addresses within 15.6
μ
s after
exiting from self-refresh mode.
Others
Power-down mode:
The SDRAM enters power-down mode when CKE goes Low in the IDLE state. In
power down mode, power consumption is suppressed by deactivating the input initial circuit. Power down
mode continues while CKE is held Low. In addition, by setting CKE to High, the SDRAM exits from the
power down mode, and command input is enabled from the next clock. In this mode, internal refresh is not
performed.
Clock suspend mode:
By driving CKE to Low during a bank-active or read/write operation, the SDRAM
enters clock suspend mode. During clock suspend mode, external input signals are ignored and the internal
state is maintained. When CKE is driven High, the SDRAM terminates clock suspend mode, and
command input is enabled from the next clock. For details, refer to the "CKE Truth Table".
Power-up sequence:
The SDRAM should be gone on
the following sequence with power up.
The CLK, CKE,
CS
, DQM, DQMU/DQML and DQ pins keep low till power stabilizes.
The CLK pin is stabilized within 100
μ
s after power stabilizes before the following initialization sequence.
The CKE and DQM, DQMU/DQML is driven to high between power stabilizes and the initialization
sequence.
This SDRAM has V
CC
clamp diodes for CLK, CKE,
CS
, DQM, DQMU/DQML and DQ pins. If these pins
go high before power up, the large current flows from these pins to V
CC
through the diodes.
Initialization sequence:
When 200
μ
s or more has past after the above power-up sequence, all banks must
be precharged using the precharge command (PALL). After t
RP
delay, set 8 or more auto refresh commands
(REF). Set the mode register set command (MRS) to initialize the mode register. We recommend that by
keeping DQM, DQMU/DQML to High, the output buffer becomes High-Z during Initialization sequence,
to avoid DQ bus contention on memory system formed with a number of device.
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| HM5264405F | 64M LVTTL interface SDRAM(64M LVTTL接口同步DRAM) |
| HM5264805F-75 | Circular Connector; MIL SPEC:MIL-C-26482, Series I, Solder; Body Material:Aluminum; Series:PT06; No. of Contacts:36; Connector Shell Size:22; Connecting Termination:Solder; Circular Shell Style:Straight Plug; Body Style:Straight |
| HM5264805F-A60 | Circular Connector; MIL SPEC:MIL-C-26482, Series I, Solder; Body Material:Aluminum; Series:PT06; No. of Contacts:36; Connector Shell Size:22; Connecting Termination:Solder; Circular Shell Style:Straight Plug; Body Style:Straight |
| HM5264805F-B60 | Circular Connector; MIL SPEC:MIL-C-26482, Series I, Solder; Body Material:Aluminum; Series:PT06; Number of Contacts:36; Connector Shell Size:22; Connecting Termination:Solder; Circular Shell Style:Straight Plug; Body Style:Straight |
| HM5264165A60 | 64M LVTTL interface SDRAM 133 MHz/100 MHz |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| HM5264805DLTT-80 | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:x8 SDRAM |
| HM5264805DLTT-B60 | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:x8 SDRAM |
| HM5264805DTT-80 | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:x8 SDRAM |
| HM5264805DTT-B60 | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:x8 SDRAM |
| HM5264805F | 制造商:HITACHI 制造商全稱:Hitachi Semiconductor 功能描述:64M LVTTL interface SDRAM 133 MHz/100 MHz |
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